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freescale semiconductor data sheet: technical data document number: imx28cec rev. 1, 04/2011 i.mx28 package information plastic package case 5284 14 x 14 mm, 0.8 mm pitch ordering information see ta b l e 1 on page 3 for ordering information. ? freescale semiconductor, inc., 2011. all rights reserved. 1 introduction the i.mx28 is a low-power, high-performance applications processor opt imized for the general embedded industrial and consumer markets.the core of the i.mx28 is freescale's fast, power-efficient implementation of the arm926ej-s? core, with speeds of up to 454 mhz. the device is suitable for a wide range of applications, including the following: ? human-machine interface (hmi) panels: industrial, home ? industrial drive, plc, i/o control display, factory robotics displa y, graphical remote controls ? handheld scanners and printers ? patient-monitoring, portable medical devices ? smart energy meters, energy gateways ? media phones, media gateways the integrated power ma nagement unit (pmu) on the i.mx28 is composed of a triple output dc-dc switching converter and mult iple linear regulators. these provide power sequencing for the device and its i/o peripherals such as memories and sd cards, as well as provide battery charging capability for li-ion batteries. i.mx28 applications processors data sheet for consumer products silicon version 1.2 contents 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. device features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. ordering information & functional part differences 3 1.3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1. special signal considerations . . . . . . . . . . . . . . . 10 3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. i.mx28 device-level conditions . . . . . . . . . . . . . . 11 3.2. thermal characteristics . . . . . . . . . . . . . . . . . . . . 19 3.3. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4. i/o ac timing and parameters . . . . . . . . . . . . . . . 24 3.5. module timing and electrical parameters . . . . . . 28 4. package information and contact assignments . . . . . . . 60 4.1. 289-ball mapbga?case 14 x 14 mm, 0.8 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2. ground, power, sense, and reference contact assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3. signal contact assignments . . . . . . . . . . . . . . . . . 62 4.4. i.mx287 ball map . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5. i.mx286 ball map . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6. i.mx283 ball map . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.7. i.mx280 ball map . . . . . . . . . . . . . . . . . . . . . . . . . 68 5. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
i.mx28 applications processors data sh eet for consumer products, rev. 1 2 freescale semiconductor the i.mx28 processor includes an additional 128-kbyt e on-chip sram to make the device ideal for eliminating external ram in applic ations with small footprint rtos. the i.mx28 supports connections to va rious types of external memories , such as mobile ddr, ddr2 and lv-ddr2, slc and mlc nand flash. the i.mx28 can be connected to a variety of extern al devices such as high-speed usb2.0 otg, can, 10/100 ethernet, and sd/sdio/mmc. 1.1 device features the following lists the features of the i.mx28: ? arm926ej-s cpu running at 454 mhz: ? 16-kbyte instruction cache and 32-kbyte data cache ? arm embedded trace macr ocell (coresight? etm9?) ? parallel jtag interface ? 128 kbytes of integrated low-power on-chip sram ? 128 kbytes of integrated ma sk-programmable on-chip rom ? 1280 bits of on-chip one-ti me-programmable (ocotp) rom ? 16-bit mobile ddr (mddr) (1.8 v), ddr2 (1.8 v) and lv-d dr2 (1.5 v), up to 205 mhz ddr clock frequency with voltage overdrive ? support for up to eight nand flash memory devices with up to 20-bit bch ecc ? four synchronous serial ports (ssp) for sdio/mmc/ms/spi. two can be used for sdio/mmc/ms interfaces (supports sd2.0, emmc4.4 and mspro), and all can be used for the spi interface. ? 10/100-mbps ethernet mac compat ible with ieee std 802.3?, supporting ieee std 1588?-compatible hardware timestam p. also supports 50-mhz/25-mhz clock output for external ethernet phy. ? two 2.0b protocol-compatible contro ller area network (can) interfaces ? one usb2.0 otg device/ host controller and phy ? one usb2.0 host controller and phy ? lcd controller, up to 24-bit rgb (dotck) modes and 24-bit system-mode ? pixel-processing pipeline (pxp) supports full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access. ? spdif transmitter ? dual serial audio interface (sai f) to support full-duplex transm it and receive operations; each saif supports three stereo pairs ? five application universal asynchronous receiver -transmitters (uarts), up to 3.25 mbps with hardware flow control ? one debug uart operating at up to 115 kb/s using programmed i/o ?two i 2 c master/slave interfaces, up to 400 kbps ? four 32-bit timers and a rotary decoder
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 3 ? eight pulse width modulators (pwms) ? real-time clock (rtc) ? gpio with interrupt capability ? power management unit (pmu) supports a triple output dc-d c switching converter, multiple linear regulators, battery charger, and detector. ? 16-channel low-resolution a/d converter (lradc) ? 4/5-wire touchs creen controller ? up to 8x8 keypad matrix wi th button-detect circuit ? single channel high speed a/d convert er (hsadc), up to 2 msps data rate ? security features: ? read-only unique id for digital rights management (drm) algorithms ? secure boot using 128-bit aes hardware decryption ? sha-1 and sha256 hashing hardware ? high assurance boot (hab4) ? offered in 289-pin ball grid array (bga) 1.2 ordering information & f unctional part differences table 1 provides the ordering information for the i.mx28. table 1. ordering information table 2 provides the functional differences between the i.mx280, i.mx283, i.mx286, and the i.mx287. part number projected temperature range ( c) package mcimx280dvm4b ?20 to +70 14 x 14 mm, 0.8mm pitch, mapbga-289 mcimx280cvm4b ?40 to +85 14 x 14 mm, 0.8mm pitch, mapbga-289 mcimx283dvm4b ?20 to +70 14 x 14 mm, 0.8 mm pitch, mapbga-289 mcimx283cvm4b ?40 to +85 14 x 14 mm, 0.8 mm pitch, mapbga-289 mcimx286dvm4b ?20 to +70 14 x 14 mm, 0.8 mm pitch, mapbga-289 MCIMX286CVM4B ?40 to +85 14 x 14 mm, 0.8 mm pitch, mapbga-289 mcimx287cvm4b ?40 to +85 14 x 14 mm, 0.8 mm pitch, mapbga-289 table 2. i.mx28 functional differences function i.mx280 i.mx283 i.mx286 i.mx287 lcd interface ? yes yes yes touch screen ? yes yes yes ethernet x1 x1 x1 x2 l2 switch ? ? ? yes can ? ? x2 x2 12-bit adc x8 x8 x8 x8
i.mx28 applications processors data sh eet for consumer products, rev. 1 4 freescale semiconductor high-speed adc x1 x1 x1 x1 usb 2.0 otg hs with hs phy x1 otg hs with hs phy x1 otg hs with hs phy x1 otg hs with hs phy x1 hs host with hs phy x1 hs host with hs phy x1 hs host with hs phy x1 hs host with hs phy x1 sdio x4 x4 x4 x4 spi x4 x4 x4 x4 application uart x6 x5 x5 x5 debug uart x1 x1 x1 x1 pwm ? x8 x8 x8 s/pdif tx ? ? yes yes s e c u r t i y ye s ye s ye s ye s table 2. i.mx28 functional differences (continued) function i.mx280 i.mx283 i.mx286 i.mx287
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 5 1.3 block diagram figure 1 shows the simplified interface block diagram. figure 1. i.mx28 simplified interface block diagram 2features table 3 shows the device functions. table 3. i.mx28 functions function bga289 external memory interface (emi) (1.5 v lv-ddr2, 1.8 v ddr2, 1.8 v lp-ddr1) ye s general-purpose media interface (gpmi): ? nand data width ? number of external nands supported 8-bit 4 dedicated / 8 with muxing pulse width modulator (pwm) 5 dedicated / 8 with muxing
i.mx28 applications processors data sh eet for consumer products, rev. 1 6 freescale semiconductor table 4 describes the digital and an alog modules of the device. application uart (auart): interfaces supported 4 dedicated / 5 with muxing synchronous serial port (ssp): supported through d edicated pins 3 dedicated / 4 with muxing i 2 c 1 dedicated / 2 with muxing spdif 1 saif 2 flexcan 2 lcd interface 24 bits high-speed adc yes lradc (touchscreen, keypad...) yes ethernet mac and switch 2 macs with switch universal serial bus (usb) 2 table 4. i.mx28 digital and analog modules block mnemonic block name subsystem brief description apbhdma ahb to apbh bridge with dma system control the ahb to apbh bridge with dma includes the ahb-to-apb pio bridge for memory-mapped i/o to the apb devices, as well a central dma facility for devices on this bus. the bridge provides a peripheral attachment bus running on the ahb?s hclk. (the ?h? in apbh denotes that the apbh is synchronous to hclk, as compared to apbx, whic h runs on the crystal-derived xclk.) the dma controller transfers read and write data to and from each peripheral on apbh bridge. apbxdma ahb to apbx bridge with dma system control the ahb-to -apbx bridge includes the ahb-to-apb pio bridge for memory-mapped i/o to the apb devices, as well a central dma facility for devices on this bus. the ahb-to -apbx bridge provides a peripheral attachment bus running on the ahb?s xclk. (the ?x? in apbx denotes that the apbx runs on a crystal-derived cloc k, as compared to apbh, which is synchronous to hclk.) the dma controller transfers read and write data to and from each peripheral on apbx bridge. arm9 or arm926 arm926ej-s cpu arm ? the arm926 platform consists of the arm926ej-s? core and the etm real-time debug modules. it contains th e 16-kbyte l1 instruction cache, 32-kbyte l1 data cache, 128-kbyte rom and 128-kbyte ram. auart(5) application uart interface connectivity peripherals each of the uart modules supports the following serial data transmit/receive protocols and configurations: ? 7- or 8-bit data words, one or two stop bits, programmable parity (even, odd, or none) ? programmable baud rates up to 3.25 mhz. this is a higher maximum baud rate than the 1.875 mhz specif ied by the tia/eia-232-f standard and previous freescale uart modules. 16-byte fifo on tx and 16-byte fifo on rx supporting auto-baud detection table 3. i.mx28 functions (continued) function bga289
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 7 bch bit-correcting ecc accelerator connectivity peripherals the bose, ray-chaudhuri, hocquenghem (bch) encoder and decoder module is capable of correcting from 2 to 20 single bit errors within a block of data no larger than about 900 bytes (512 bytes is typical) in applications such as protecting data and resources stored on modern nand flash devices. bsi boundary scan interface connectivity peripherals the boundary scan interface is provided to enable board level testing. there are five pins on the device which is used to implement the ieee std 1149.1? boundary scan protocol. clkctrl clock control module clocks the clock control module, or clkctrl, generates the clock domains for all components in the i.mx28 system. the cryst al clock or pll clock are the two fundamental sources used to produce most of the clock domains. for lower performance and reduced power consumpt ion, the crystal cl ock is selected. the pll is selected for higher performance requirements but requires increased power consumption. in most cases, when the pll is used as the source, a phase fractional divider (pfd) can be programmed to reduce the pll clock frequency by up to a factor of 2. dcp data co-processor security this module provides support for general encryption and hashing functions typically used for security functions. because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the dma-based approach. dflpt default first-level page table system control the dflpt provides a uni que method of implementing the arm mmu first-level page table (l1pt) using a hardware-based approach. digctl digital control and on-chip ram system control the digital control module includes sections for controlling the sram, the performance monitors, high-entropy pseudo-random number seed, free-running microseconds counter, and other chip control functions. duart debug uart connectivity peripherals the debug uart performs the following data conversions: ? serial-to-parallel conversion on data received from a peripheral device ? parallel-to-serial conversion on data transmitted to the peripheral device emi external memory interface connectivity peripherals the i.mx28 supports off-chip dram st orage through the emi controller, which is connected to the four intern al ahb/axi busses. the emi supports multiple external memory types, including: ? 1.8-v mobile ddr1 (lp-ddr1) ? standard 1.8-v ddr2 ? low voltage 1.5-v ddr2 (lv-ddr2) enet ethernet mac controller connectivity peripherals ethernet mac controller connected to the udma (unified dma). supports 10/100 mbps with tcp/udp/ip acceleration and ieee 1588 functions; also supports rmii or mii connectivity. flexcan(2) controller area network module connectivity peripherals the controller area network (can) prot ocol is a message based protocol used for serial data. it was designed specifically for automotive but is also used in industrial control and medical applications. the serial data bus runs at 1 mbps. gpmi general-pur- pose media interface connectivity peripherals the general-purpose media interface (gpmi) controller is a flexible nand flash controller with 8-bit data width, up to 50-mbps i/o speed and individual chip select and dma channels for up to 8 nand devices. it also provides a interface to 20-bit bch for ecc. table 4. i.mx28 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx28 applications processors data sh eet for consumer products, rev. 1 8 freescale semiconductor hsadc high-speed adc connectivity peripherals the high-speed adc block is designed to sample an analog input with 12-bit resolution and a sample rate of up to 2 msps. the output of the hsadc block can be moved to the external memory through apbh-dma. a typical user case of the hsadc is to work with the pwm block to drive an external linear image scanner sensor. i 2 c(2) i 2 c module connectivity peripherals the i 2 c is a standard two-wire serial interf ace used to connect the chip with peripherals or host controllers. the i 2 c operates up to 400 kbps in either i 2 c master or i 2 c slave mode. each i 2 c has a dedicated dma channel and can also controlled by cpu in pio or pio queue modes. it supports both 7-bit and 10-bit device address in master mode, and has programmable 7-bit address in slave mode. icoll interrupt collector system control the arm9 cpu core has two inte rrupt input lines, irq and fiq. the interrupt collector (icoll) can steer any of 128 interrupt sources to either the fiq or irq line of the arm9 cpu. l2 switch 3-port l2 switch network control programmable 3-port ethernet switch with qos lcdif lcd interface multimedia peripherals the lcdif provides display data for external lcd panels from simple text-only displays to wvga, 16/18/24 bpp color tft panels. the lcdif supports all of these different interfaces by providing fully programmable functionality and sharing register s pace, fifos, and alu resources at the same time. the lcdif supports rgb (dotclk) modes as well as system mode including both vsync and wsync modes. lradc low resolution adc module connectivity peripherals the sixteen-channel 12-bit low-resolution adc (lradc) block is used for voltage measurement. channels 0 ? 6 measure the voltage on the seven application-dependent lradc pins. the auxiliary channels can be used for a variety of uses, including a resistor-divider-based wired remote control, external temperature sensing, to uch-screen, and other measurement functions. ocotp controller on-chip otp controller security the on-chip one-time-programmable (ocotp) rom serves the functions of hardware and software capability bits, freescale operations and unique-id, the customer-programmable cryptography key, and storage of various rom configuration bits. pinctrl pin control and gpio system control peripherals used for general purpose input/output to external ics. each gpio bank supports 32 bits of i/o. table 4. i.mx28 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 9 pmu power management unit (dc-dc) power management system the i.mx28 integrates a comprehensiv e power supply subsystem, including the following features: ? one integrated dc-dc converter that supports li-ion battery. ? four linear regulators directly power the supply rails from 5-v. ? linear battery charger for li-ion cells. ? battery voltage and brownout detection monitoring for vddd, vdda, vddio, vdd4p2 and 5-v supplies. ? integrated current limiter from 5-v power source. ? reset controller. ? system monitors for temperature and speed. ? generates usb-host 5-v from li-ion battery (using pwm). ? support for on-the-fly transitioning between 5-v and battery power. ? vdd4p2, a nominal 4.2-v supply, is available when the i.mx28 is connected to a 5-v source and allows the dcdc to run from a 5-v source with a depleted battery. ? the 4.2-v regulated output also allows for programmable current limits: ? battery charge current + dcdc input current < the 5-v current limit ? dcdc input current (which ultimately provides current to the on-chip and off-chip loads) as the priority and battery charge current is automatically reduced if the 5-v current limit is reached pwm(8) pulse width modulation connectivity peripherals there are eight pwm output controllers that can be used in place of gpio pins. applications include hsadc driving signals and led & backlight brightness control. independent output cont rol of each phase allows 0, 1, or high-impedance to be independently selected for the active and inactive phases. individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. pxp pixel pipeline multimedia the pixel pipeline (pxp) is used to perform alpha blending of graphic or video buffers with graphics data before send ing to an lcd display. the pxp also supports image rotation for hand-held devices that require both portrait and landscape image support. rtc real-time clock, alarm, watchdog clocks the real-time clock (rtc) and alarm share a one-second pulse time domain. the watchdog reset and millisecond counter run on a one-millisecond time domain. the rtc, alarm, and persistent bits reside in a special power domain (crystal domain) that remains powered up even when the rest of the chip is in its powered-down state. saif(2) serial audio interface connectivity peripherals saif provides a half-duplex serial port for communication with a variety of serial devices, including industry-standard codecs and dsps. it supports a continuous range of sample rates from 8 khz?192 khz using a high-resolution fractional divider driven by the pll. samples are transferred to/from the fifo through the apbx dma in terface, a fifo service interrupt, or software polling. spdif spdif connectivity peripherals the sony-philips digital interface format (spdif) transmitter module transmits data according to the spdif digital audio interface standard (iec-60958). table 4. i.mx28 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx28 applications processors data sh eet for consumer products, rev. 1 10 freescale semiconductor 2.1 special signal considerations special signal considerat ions are listed in table 5 . the package contact a ssignment is found in section 4, ?package information and contact assignments .? signal descriptions are provided in the reference manual. ssp(4) synchronous serial port connectivity peripherals the synchronous serial port is a flexible interface for inter-ic and removable media control and commun ication. the ssp supports master operation of spi, texas instruments ssi; 1-bit, 4-bi t, and 8-bit sd/sdio/mmc and 1-bit and 4-bit ms modes. the spi mode has enhancements to support 1-bit legacy mmc cards. spi master dual (2-bit) and quad (4-bit) mode reads are also supported. the ssp also supports slave operation for the spi and ssi modes. the ssp has a dedicated dma channel in the bridge and can also be controlled directly by the cpu through pio registers. each of the four ssp modules is independent of the other and can have separate sspclk frequencies. timrot timers and rotary decoder timer peripherals this module implements four timers and a rotary decoder. the timers and decoder can take their inputs from any of the pins defined for pwm, rotary encoders, or certain divisions from the 32-khz clock input. thus, the pwm pins can be inputs or output s, depending on the application. usbotg usbhost high-speed usb on-the-go connectivity peripherals the usb module provides high-performance usb on-the-go (otg) and host functionality (up to 480 mbps), co mpliant with the usb 2.0 specification and the otg supplement. the module has dma capabilities for handling data transfer between internal buffers and system memory. when the otg controller works in device mode, it can only work in fs or hs mode. two usb2.0 phys are also integrated (one for the otg port, another for the host port.) usbphy integrated usb phy connectivity peripherals the integrated usb 2.0 phy macrocells are capable of connecting to usb host/device systems at the usb low-spe ed (ls) rate of 1.5 mbps, full-speed (fs) rate of 12 mbps or at the usb 2.0 high-speed (hs) rate of 480 mbps. the integrated phys provide a standard utm interface. the usb_dp and usb_dn pins connect directly to a usb connector. table 5. signal considerations signal descriptions pswitch the pin is used for chip power on or recovery. vddio can be applied to pswitch through a 10 k resistor. this is necessary in order to ente r the chip?s firmware recovery. the on-chip circuitry prevents the actual voltage on the pin from exceeding acceptable levels. vddxtal this pin is an output of i.mx28. should be coupled to ground with a 0.1 uf capacitor. user should not supply external power to this pin. battery this pin should be connected to the battery wit h minimal resistance. it provides charging current to the battery. see the ?power supply? section of the reference manual for details. table 4. i.mx28 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 11 3 electrical characteristics this section provides the device-level and module- level electrical charact eristics for the i.mx28. 3.1 i.mx28 device-level conditions this section provides the device-level electrical characteristics for the ic. 3.1.1 dc absolute maximum ratings table 7 provides the dc absolute maximum operating conditions. caution ? stresses beyond those listed under table 7 may cause permanent damage to the device. ? exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ? table 6 gives stress ratings only?functi onal operation of the device is not implied beyond the conditions indicated in table 8 . dcdc_battery this pin is an input of i.mx28 that provides supply to the dcdc converter. it should be connected to the battery with minimal resist ance. see the ?power supply? section of the reference manual for details. xtali xtalo these analog pins are connected to an external 24 mhz crystal circuit. this crystal provides the clock source for on-chip plls. rtc_xtalo rtc_xtali these analog pins are connected to an external 32.768/32.0 khz crystal circuit. this crystal provides clock source to the on- chip real-time counter circuits. resetn this pin resets the chip if it is low. this pin is pulled up to vddio33 with an internal 10 kohm resistor. no external pull up resistors are needed. debug this pin is used for jtag interface. debug=0: jtag interface works for boundary scan. debug=1: jtag interface works for arm debugging. testmode for freescale factory use only. must be ex ternally connected to gnd for normal operation. table 6. dc absolute maximum ratings parameter symbol min. max. units battery pin batt, v dd4p2v ?0.3 4.242 v 5-volt source pin - transient , t<30ms, duty cycle <0.05% v dd5v ?0.3 7.00 v 5 volt source pin - static v dd5v ?0.3 6.00 v pswitch 1 ??0.3batt/2v table 5. signal considerations (continued) signal descriptions
i.mx28 applications processors data sh eet for consumer products, rev. 1 12 freescale semiconductor table 7 shows the electrostatic discharge immunity. note that hbm and cdm pa ss esd testing per aec-q100. analog supply voltage v dda ?0.3 2.10 v digital core supply voltage v ddd ?0.3 1.575 v non-emi digital i/o supply v ddio ?0.3 3.63 v emi digital i/o supply v ddio.emi ?0.3 3.63 v dc-dc converter 2 dcdc_batt ?0.3 batt v input voltage on any digital i/o pin relative to ground ? ?0.3 vddio+0.3 v input voltage on usb_dp and usb_dn pins relative to ground 3 ??0.33.63v analog i/o absolute maximum rati ngs (exceptions: xtali, xtalo, rtc_xtali, rtc_xtalo) ? ?0.3 vddio+0.3 v storage temperature ? ?40 125 c 1 vddio can be applied to pswitch through a 10 k resistor. this is necessary in order to enter the chip?s firmware recovery mode. (the on-chip circuitry prevents the actual vo ltage on the pin from exceeding acceptable levels.) 2 application should include a schottky diode between batt and vdd4p2. 3 usb_dn and usb_dp can tolerate 5v for up to 24 hours. note that while 5v is applied to usb_dn or usb_dp, lradc readings can be corrupted. table 7. electrostatic discharge immunity 289-pin bga package tested level human body model (hbm) 2 kv charge device model (cdm) 500 v table 6. dc absolute maximum ratings (continued) parameter symbol min. max. units
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 13 3.1.2 dc operating conditions table 8 provides the dc recomme nded operating conditions. table 9 provides the dc operati ng temperature conditions. table 8. recommended power supply operating conditions parameter symbol min typ max units analog core supply voltage v dda 1.62 ? 2.10 v digital core supply voltage specification dependent on frequency. 1, 2 1 for optimum usb jitter performance, v ddd = 1.35 v or greater. 2 v ddd supply minimum voltage includes 75 mv guardband. v ddd 1.35 ? 1.55 v digital supply voltages: ? vddio33/vddio33_emi ? vddio18 v ddio33 /v ddio33_emi /v ddi o18 3.0 1.7 ? ? 3.6 1.9 v emi digital i/o supply voltage: ? ddr2/mddr ? lvddr2 v ddio.emi /v ddio_emiq 1.7 1.425 1.8 1.5 1.9 1.625 v battery / dcdc input voltage - batt, dcdc_batt batt dcdc_batt 3.10 3 3 tested with only the i.mx28 processor loading the mx28 pmu output rails during start up. ?4.242 v vdd5v supply voltage (5 v current < 100 ma) ? tbd 5.00 5.25 v vdd5v supply voltage (5v current 100 ma) ? 4.75 5.00 5.25 v offstate current: 4 4 when the real-time clock is enabled, the chip consumes additiona l current in the off state to keep the crystal oscillator and the real-time clock running. ? 32-khz rtc off, batt = 4.2 v ? ? 11 30 a ? 32-khz rtc on, batt = 4.2 v ? ? 13.5 30 a table 9. operating temperature conditions parameter symbol min typ max units commercial ambient operating temperature range 1, 2 1 in most portable systems designs, battery and display specifications limits the operating range to well within these specifications. most battery manufactur ers recommend enabling battery charge on ly when the ambient temperature is between 0c and 40c. to ensure that battery charging does not occur outside the recommended temperature range, the system ambient temperature may be monitored by connecting a thermistor to the lradc0 or lradc6 pin on the i.mx28. t a ?20 ? 70 c commercial junction temperature range 1, 2 t j ?20 ? 85 c industrial ambient operating temperature range 1, 2 t a ?40 ? 85 c industrial junction temperature range 1, 2 t j ?40 ? 105 c
i.mx28 applications processors data sh eet for consumer products, rev. 1 14 freescale semiconductor table 10 provides the recommended analog operating conditions. table 11 shows the pswitch input characteristics. see the reference schematics for the recommended pswitch button circuitry. table 12 shows the power consumption. 2 maximum ambient operating tem perature may be limited due to on-chip power dissipation. t a (max) t j - ( ja x p d ) where: t j = maximum junction temperature ja = package thermal resistance. see section 3.2, ?thermal characteristics .? p d = total on-chip power dissipation =pvdd4p2 + pbatteryc harger + pdcdc + plinearregulat ors + pinternal. depending on the application, some of these po wer dissipation terms may not apply. pvdd4p2 = vdd4p2 on-chip power dissipation = (vdd5v - vdd4p2) x idd4p2 pbatterycharger = battery charger on-chip powe r dissipation = (vdd5v - batt) x icharge pdcdc = dc-dc converter on-chip power dissipation = (batt x dcdc input current) x (1 - efficiency) plinearregulators = linear regulator on-chip power dissi pation = (vdd5v - vddio) x (iddio + idda + iddd + idd1p5) + (vddio - vdda) x (idda + iddd) + (vdda - vddd) x iddd + (vdda - vdd1p5) x idd1p5 pinternal = internal digital on-chip power dissipation = ~vddd x iddd table 10. recommended analog operating conditions parameter min typ max units low resolution adc input impedance (ch0 - ch5) >1 ? ? m table 11. pswitch input characteristics parameter hw_pwr_sts_ pswitch min max units pswitch low level 0x00 0.00 0.30 v pswitch mid level & startup 1 1 a mid level pswitch state can be generated by connecting the vddxtal output of the soc to pswitch through a switch. 0x01 0.65 1.50 v pswitch high level 2 2 pswitch acts like a high impedance input (>300 k ) when the voltage applied to it is less than 1.5v. however, above 1.5v it becomes lower impedance. to simplify design, it is recommended that a 10 k resistor to vddio be applied to pswitch to set the high level state (the pswit ch input can tolerate voltages greater t han 2.45 v as long as there is a 10 k resistor in series to limit the current). 0x11 (1.1 * vddxtal) + 0.58 2.45 v table 12. power consumption parameter min typ max units power consumption: conditions - tbd ? tbd ? mw
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 15 table 13 illustrates the power supply characteristics. table 13. power supply characteristics parameter min typ max units linear regulators output voltage accuracy (v ddio , v dda , v ddm , v ddd ) 1 1 no load. ?3 ? +3 % v ddio maximum output current (v ddio = 3.30 v, v dd5v =4.75v) 2, 3 2 maximum output current measured when output voltage droo ps 100 mv from the programmed target voltage with no load present. 3 because the internal linear regulators are cascaded, it is not possible to simultaneously operate the v ddio , v dda , v ddm , and v ddd linear regulators at the maximum specified load current. for example, the v ddio linear regulator provides current to both the v ddio 3.3 v supply rail as well as the v ddm and v dda linear regulator inputs. likewise, the v dda linear regulator provides current to both the 1.8 v supply rail as well as the v ddd linear regulator input. the application designer should ensure the following two conditions are met: (v ddio load current + v ddm load current + v dda load current) < v ddio maximum output current (v dda load current + v ddd load current) < v dda maximum output current 270 ? ? ma v ddio maximum output current (v ddio = 3.30 v, v dd5v = 4.40 v) 2, 3 200 ? ? ma v ddm maximum output current (v ddm = 1.5 v) 2 160 ? ? ma v dda maximum output current (v dda =1.8v) 2, 3 225 ? ? ma v ddd maximum output current (v ddd =1.2v) 2, 3 200 ? ? ma dcdc converters output voltage accuracy (dcdc_vddio, dcdc_vdda, dcdc_vddd) 1 ?3 ? +3 % dcdc_vddd maximum output current (v ddd = 1.55 v) 4, 5 4 dcdc double fets enabled, inductor value = 15 h. 5 the dcdc converter is a triple output buck converter. the maximu m output current capability of each output of the converter is dependent on the loads on the other two out puts. for a given output, it may be possible to achieve a maximum output current higher than that specified by ensuring the load on the other outputs is well below the maximum. 250 ? ? ma dcdc_vdda maximum output current (v dda =1.8v) 4, 5 200 ? ? ma dcdc_vddio maximum output current (v ddio = 3.15 v, 3.3 v < batt < 4.242 v) 4, 5, 6 6 assumes simultaneous load of iddd = 25 0 ma@ 1.55 v and idda = 200 ma@1.8 v. 250 ? ? ma vdd4p2 regulated output vdd4p2 output voltage accuracy (target=4.2v) 1 ?3 ? +3 % vdd4p2 output current limit accuracy (vdd5v = 4.75 v, ilimit=480 ma) 7 tbd 480 tbd ma vdd4p2 output current limit accuracy (vdd5v=4.75 v, ilimit=100 ma) 7 tbd 100 tbd ma battery charger final charge voltage accuracy (target=4.2 v) -2 ? +1 %
i.mx28 applications processors data sh eet for consumer products, rev. 1 16 freescale semiconductor 3.1.2.1 recommended operating conditions for specific clock targets table 14 through table 18 provide the recommended operating c onditions for specific clock targets. 7 untuned. table 14. system clocks name min. freq. (mhz) max. freq. (mhz) description clk_gpmi ? tbd general purpose memory interface clock domain clk_ssp ? tbd ssp interface clock domain table 15. recommended operating states?289-pin bga package vddd (v) vddd brown-out (v) hw_ digctrl armcach e 1 1 all timing control bit fields in hw_digctrl_armcache should be set to the same value. cpuclk / clk_p frequency (mhz) hw_ clkctrl cpu_div_cp u hw_ clkctrl frac_ cpufrc / pfd ahbclk / clk_h frequency (mhz) hw_ clkctrl hbus_di v emiclk / clk_emi frequency (mhz) hw_ clkctrl emi_ div_emi hw_ clkctrl frac_ emifrac supported dram tbd tbd 00 64 5 27 64 1 130.91 2 33 ddr2 mddr 1.350 1.250 00 261.81 1 33 130.91 2 130.91 2 33 ddr2 mddr 1.350 1.250 00 360 1 24 120.00 3 130.91 2 33 ddr2 mddr 1.450 1.350 00 392.72 1 22 130.91 3 160.00 2 27 ddr2 mddr 1.550 1.450 00 454.73 1 19 151.57 3 205.71 2 21 ddr2 mddr table 16. recommended operating conditions?cpu clock (clk_p) minimum vddd (v) minimum vddd brown-out (v) hw_digctrl armcache 1 1 all timing control bit fields in hw_digctrl_armcache should be set to the same value. hw_clkctrl frac_cpufrc / pfd cpuclk / clk_p frequency max (mhz) tbd tbd 00 27 - 35 tbd 1.350 1.250 00 18 - 35 360 1.450 1.350 00 18 - 35 392.72 1.550 1.450 00 18 - 35 454.73
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 17 3.1.3 fusebox supply current parameters table 19 lists the fusebox supply current parameters. 3.1.4 interface frequency limits table 20 provides information for interface frequency limits. table 17. recommended operating conditions?ahb clock (clk_h) minimum vddd (v) minimum vddd brown-out (v) hw_digctrl armcache 1 1 all timing control bit fields in hw_digctrl_armcache should be set to the same value. hw_clkctrl frac_cpufrc / pfd ahbclk / clk_h frequency max (mhz) tbd tbd 00 27 - 35 tbd 1.350 1.250 00 18 - 35 160 1.450 1.350 00 18 - 35 196 1.550 1.45 00 18 - 35 206 table 18. frequency vs. voltage for emiclk?289-pin bga package minimum vddd (v) minimum vddd brownout (v) emiclk fmax (mhz) ddr2 mddr 1.550 1.450 205.71 205.71 1.450 1.350 196.36 196.36 1.350 1.250 196.36 196.36 table 19. fusebox supply current parameters parameter symbol min typ max units efuse program current 1 current to program one efuse bit efuse_vddq=2.5v 1 the current i program is during program time. i program 21.39 25.05 33.54 ma efuse read current 2 current to read an 8-bit efuse word vdd_fusebox = 3.3 v 2 the current i read is present for approximately 10 ns of the read access to the 8-bit word. i read ? ? 4.07 ma table 20. interface frequency limits parameter min. typ. max. units jtag: tck frequency of operation ? ? 10 mhz osc24m_xtal oscillator ? 24.000 ? mhz osc32k_xtal oscillator ? 32.768/32.0 ? khz
i.mx28 applications processors data sh eet for consumer products, rev. 1 18 freescale semiconductor 3.1.5 power modes table 21 describes the core, clock, and module settings for the different power modes of the processor. 3.1.6 supply power-up/power-down requirements there is no special power-up sequence. after applying 5 v or battery in any order, the rest of the power supplies are internally generated and automatically come up in a safe way. there is no special power-down sequence. 5 v or the battery can be removed at any time. 3.1.7 reset timing because the i.mx28 is a pmu and an soc, power-on re set is generated internal ly and there is no timing requirement on external pins. the i.mx28 can be reset by asserti ng the external pin resetn for at least 100 ms and later deasserting resetn. if the reset occurs while the device is only powered by the battery, then the reset kills all of the power supplies and the system reboots on the assertion of pswitch. if auto-resta rt is set up ahead of time, the system reboots immediately. if the chip is powered by 5 v, then th e reset serves to reset the digital se ctions of the chip . if the dcdc is operating at the time of the reset, th en power switches back to the defa ult linear regulators powered by 5 v. figure 2. resetn timing table 21. power mode settings core/clock/module deep-sleep standby run arm core off off on usb0 pll (system pll) off off on osc24m off on on osc32k on on on dcdc off on on rtc on on on other modules off on/off on/off resetn at least 100ms
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 19 3.2 thermal characteristics the thermal resistance characteris tics for the device are given in table 22 . these values are measured under the following conditions: ? two layer substrate ? substrate solder mask thickness: 0.025 mm ? substrate metal thicknesses: 0.016 mm ? substrate core thickness: 0.160 mm ? core via i.d: 0.068 mm, core via plating 0.016 mm ? flag: trace style with ground balls under the die connected to the flag ? die attach: 0.033 mm non-conductive die attach, k = 0.3 w/m k ? mold compound: generic mold compound, k = 0.9 w/m k 3.3 i/o dc parameters this section includes the dc parame ters of the following i/o types: ? ddr i/o: mobile ddr (lpddr1), standa rd 1.8 v ddr2, and low-voltage 1.5 v ddr2 (lvddr2) ? general purpose i/o (gpio) table 22. thermal resistance data rating value unit junction to ambient 1 natural convection 1 junction-to-ambient thermal resistance determined per je dec jesd51-2 and jesd51-6. thermal test board meets jedec specification for this package. single layer board (1s) r ja 62 c/w junction to ambient 1 natural convection four layer board (2s2p) r ja 36 c/w junction to ambient 1 (@200 ft/min) single layer board (1s) r jma 53 c/w junction to ambient 1 (@200 ft/min) four layer board (2s2p) r jma 33 c/w junction to boards 2 2 junction-to-board thermal resistance determined per jede c jesd51-8. thermal test boar d meets jedec specification for the specified package. r jb 24 c/w junction to case (top) 3 3 junction-to-case at the top of the package determined using mil-std 883 method 1012.1. th e cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. r jctop 15 c/w junction to package top 4 4 thermal characterization parameter indicating the temper ature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. natural convection jt 3c/w
i.mx28 applications processors data sh eet for consumer products, rev. 1 20 freescale semiconductor 3.3.1 ddr i/o dc parameters table 23 shows the emi digital pin dc characteristics. note the current values and the i-v curves of the i/o dc characteristics are estimated based on an overly conserva tive device model. they are updated upon the measurement results of the first silicon. table 24 shows the on impedance of emi driv ers for different drive strengths. table 23. emi digital pin dc characteristics parameter symbol min. max. units input voltage high (dc) vih vref + 0.125 vddio_emi + 0.3 v input voltage low (dc) vil 0.3 vref ? 0.125 v output voltage high (dc) voh 0.8 * vddio_emi ? v output voltage low (dc) vol - 0.2 * vddio_emi v output source current (dc) lvddr2 mode ioh 1 ?low 1 ioh is the output current at whic h the voh specification is met. tbd tbd ma ioh?medium tbd tbd ma ioh?high tbd tbd ma output sink current (dc) lvddr2 mode iol 2 ?low 2 iol is the output current at wh ich the vol specification is met. tbd tbd ma iol?medium tbd tbd ma iol?high tbd tbd ma output source current (dc) mddr, ddr2 mode ioh?low tbd tbd ma ioh?medium tbd tbd ma ioh?high tbd tbd ma output sink current (dc) mddr, ddr2 mode iol?low tbd tbd ma iol?medium tbd tbd ma iol?high tbd tbd ma table 24. on impedance of emi drivers for different drive strengths mode drive min. ( )typ. ( )max. ( ) 1.5 lvddr2 low tbd tbd tbd medium tbd tbd tbd high tbd tbd tbd
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 21 table 25 shows the external devices supported by the emi. 3.3.2 gpio i/o dc parameters max load includes capacitive load due to pcb trace s, pad capacitance and driver self-loading. for the internal pull up setting of each pad, see the ?pin control and gpio? section of the reference manual. table 26 shows the digital pin dc char acteristics for gpio in 3.3-v m ode. measurements are valid for eight pins loaded using the 4ma driver, four pins lo aded using the 8ma driver, and two pins loaded using either the 12ma or 16ma driver. 1.8 ddr2/mddr low tbd tbd tbd medium tbd tbd tbd high tbd tbd tbd table 25. external devices supported by the emi dram device max load 1, 2 1 max load includes capacitive load due to pcb traces, pad capacitance and driver self-loading. 2 setting is for worst case. freescale?s emi interface uses less po werful drivers than those typically used in mddr devices. a possible transmission-line effect on the pc board must be suppressed by minimizing the trace length combined with freescale?s slower edge-rate drivers. the i.mx28 provides up to 16 ma programmable drive strength. however, the 16-ma mode is an experimental mode. with the 16-ma mode, the emi function may be impaired by simultaneous switching output (sso) noise. in general, the stronger the driver mode, the noi sier the on-chip power supply. freescale recommends not using a stronger driver mode than is required. because on-chip power and ground noise is proportional to the inductance of its return path, users should make their best effort to reduce induct ance between the emi power and ground balls and the pc board power and ground planes. pad voltage ddr2 15 pf 1.8 v mddr 15 pf 1.8 v lvddr2 15 pf 1.5 v table 26. digital pin dc characteristics for gpio in 3.3-v mode parameter symbol min max units input voltage high (dc) vih 2 vddio v input voltage low (dc) vil ? 0.8 v output voltage high (dc) voh 0.8 vddio ? v output voltage low (dc) vol ? 0.4 v output source current 1 (dc) gpio ioh ? low -5.0 ? ma ioh ? medium -9.5 ? ma ioh ? high -11.4 ? ma table 24. on impedance of emi drivers for different drive strengths (continued) mode drive min. ( )typ. ( )max. ( )
i.mx28 applications processors data sh eet for consumer products, rev. 1 22 freescale semiconductor output sink current 1 (dc) gpio iol ? low 3.8 ? ma iol ? medium 7.7 ? ma iol ? high 9.0 ? ma output source current 1 (dc) gpio_clk ioh ? low -9.2 ? ma ioh ? high -15.2 ? ma output sink current 1 (dc) gpio_clk iol ? low 7.6 ? ma iol ? high 12.0 ? ma 10-k pull-up resistance 2 rpu10k 8 12 k 47-k pull-up resistance 2 rpu47k 39 56 k 1 the conditions of the current measurements for all different drives are as follows: iol: at 0.4 v ioh: at vddio * 0.8 v maximum corner for 3.3 v mode: 3.6 v, -40 c, fast process. minimum corner for 3.3 v mode: 3.0 v, 105 c, slow process 8 gpio pins (lcd_d0-d7) and 2 gpio_clk pins (lcd_dotclk and lcd_wr_rwn) simultaneously loaded. 2 see the i.mx28 reference manual for detai led pull-up configuration of each i/o. table 26. digital pin dc characteristics for gpio in 3.3-v mode (continued) parameter symbol min max units
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 23 table 27 shows the digital pin dc charac teristics for gpio in 1.8 v mode. table 27. digital pin dc characteristics for gpio in 1.8 v mode symbol min max units input voltage high (dc) vih 0.7 vddio18 vddio18 v input voltage low (dc) vil ? 0.3 vddio18 v output voltage high (dc) voh 0.8 * vddio18 ? v output voltage low (dc) vol ? 0.2 vddio18 v output source current 1 (dc) gpio 1 the condition of the current measurements for all different drives are as follows: maximum corner for 1.8 v mode: 1.9 v, -40 c, fast process. minimum corner for 1.8 v mode: 1.7 v, 105 c, slow process. 1 gpio pin (gpmi_d0) and 1 gpio_clk pin (gpmi_wrn) simultaneously loaded. ioh ? low -2.2 ? ma ioh ? medium -3.5 ? ma ioh ? high -4.0 ? ma output sink current 1 (dc) gpio iol ? low 3.3 ? ma iol ? medium 7.0 ? ma iol ? high 7.5 ? ma output source current 1 (dc) gpio_clk ioh ? low -4.2 ? ma ioh ? high -6.0 ? ma output sink current 1 (dc) gpio_clk iol ? low 6.8 ? ma iol ? high 11.5 ? ma 10-k pull-up resistance 2 2 see the i.mx28 reference manual for detailed pull-up configuration of each i/o. rpu10k 8 12 k 47-k pull-up resistance 2 rpu47k 39 56 k
i.mx28 applications processors data sh eet for consumer products, rev. 1 24 freescale semiconductor 3.4 i/o ac timing and parameters figure 3 and figure 4 show the driver used for ac simulation testpoint and the output pad transition waveform. figure 3. driver used for ac simulation testpoint figure 4. output pad transition waveform table 28 shows the base gpio ac timing and parameters. table 28. base gpio parameters symbol test voltage test capacitance min rise/fall maxrise/fall units notes duty cycle fduty ? ? ? ? % ? output pad transition times (maximum drive) tpr 1.7~1.9v 10pf 0.82 0.91 1.93 1.97 ns ? 1.7~1.9v 20pf 1.18 1.22 2.69 2.71 ? 1.7~1.9v 50pf 2.11 2.03 4.62 4.44 ? 3.0~3.6v 10pf 1.04 1.08 2.46 2.18 ? 3.0~3.6v 20pf 1.42 1.5 3.29 3 ? 3.0~3.6v 50pf 2.46 2.61 5.34 5.12 ? driver used for ac simulation testpoint driver used for ac simulation testpoint output pad transition waveform vddio 20% 80% output pad transition waveform vddio 20% 80%
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 25 output pad transition times (medium drive) tpr 1.7~1.9v 10pf 1.02 1.08 2.34 2.38 ns ? 1.7~1.9v 20pf 1.51 1.5 3.34 3.28 ? 1.7~1.9v 50pf 2.91 2.62 6.24 5.67 ? 3.0~3.6v 10pf 1.26 1.29 2.9 2.6 ? 3.0~3.6v 20pf 1.8 1.88 4 3.67 ? 3.0~3.6v 50pf 3.3 3.46 6.91 6.64 ? output pad transition times (low drive) tpr 1.7~1.9v 10pf 1.62 1.68 3.65 3.68 ns ? 1.7~1.9v 20pf 2.55 2.45 5.59 5.37 ? 1.7~1.9v 50pf 5.42 4.62 11.46 10.01 ? 3.0~3.6v 10pf 1.95 2.12 4.43 4.25 ? 3.0~3.6v 20pf 2.96 3.21 6.36 6.25 ? 3.0~3.6v 50pf 5.89 6.39 12.02 12.18 ? output pad slew rate (maximum drive) tps 1.7~1.9v 10pf 1.39 1.25 0.53 0.52 v/ns ? 1.7~1.9v 20pf 0.97 0.93 0.38 0.38 ? 1.7~1.9v 50pf 0.54 0.56 0.22 0.23 ? 3.0~3.6v 10pf 2.08 2.00 0.73 0.83 ? 3.0~3.6v 20pf 1.52 1.44 0.55 0.60 ? 3.0~3.6v 50pf 0.88 0.83 0.34 0.35 ? output pad slew rate (medium drive) tps 1.7~1.9v 10pf 1.12 1.06 0.44 0.43 v/ns ? 1.7~1.9v 20pf 0.75 0.76 0.31 0.31 ? 1.7~1.9v 50pf 0.39 0.44 0.16 0.18 ? 3.0~3.6v 10pf 1.71 1.67 0.62 0.69 ? 3.0~3.6v 20pf 1.20 1.15 0.45 0.49 ? 3.0~3.6v 50pf 0.65 0.62 0.26 0.27 ? output pad slew rate (low drive) tps 1.7~1.9v 10pf 1.17 1.13 0.47 0.46 v/ns ? 1.7~1.9v 20pf 0.75 0.78 0.30 0.32 ? 1.7~1.9v 50pf 0.35 0.41 0.15 0.17 ? 3.0~3.6v 10pf 1.11 1.02 0.41 0.42 ? 3.0~3.6v 20pf 0.73 0.67 0.28 0.29 ? 3.0~3.6v 50pf 0.37 0.34 0.15 0.15 ? input pad average hysteresis tih 1.7 v?1.9 v ? 100 75 mv ? 3.0 v?3.6 v ? 100 50 ? table 28. base gpio (continued) parameters symbol test voltage test capacitance min rise/fall maxrise/fall units notes
i.mx28 applications processors data sh eet for consumer products, rev. 1 26 freescale semiconductor table 29 shows the f-type gpio ac timing and parameters. table 29. f-type gpio parameters symbol test voltage test capaci tance min rise/fall max rise/fall units notes duty cycle fduty ? ? ? ? % ? output pad transition times (maximum drive) tpr 1.7~1.9v 10pf 0.58 0.61 1.29 1.33 ns ? 1.7~1.9v 20pf 0.89 0.88 1.94 1.88 ? 1.7~1.9v 50pf 1.83 1.59 3.88 3.39 ? 3.0~3.6v 10pf 0.71 0.68 1.47 1.34 ? 3.0~3.6v 20pf 1.02 1.04 2.11 1.99 ? 3.0~3.6v 50pf 1.98 2.09 3.97 3.96 ? output pad transition times (medium drive) tpr 1.7~1.9v 10pf 0.76 0.76 1.68 1.61 ns ? 1.7~1.9v 20pf 1.23 1.13 2.63 2.38 ? 1.7~1.9v 50pf 2.66 2.18 5.61 4.6 ? 3.0~3.6v 10pf 0.9 0.88 1.84 1.7 ? 3.0~3.6v 20pf 1.36 1.4 2.76 2.67 ? 3.0~3.6v 50pf 2.85 3.02 5.59 5.67 ? output pad transition times (low drive) tpr 1.7~1.9v 10pf 1.32 1.26 2.88 2.72 ns ? 1.7~1.9v 20pf 2.27 1.98 4.84 4.23 ? 1.7~1.9v 50pf 5.23 4.13 10.95 8.8 ? 3.0~3.6v 10pf 1.46 1.55 3.05 3 ? 3.0~3.6v 20pf 2.46 2.62 4.92 5.02 ? 3.0~3.6v 50pf 5.56 5.96 10.78 11.22 ? output pad slew rate (maximum drive) tps 1.7~1.9v 10pf 1.97 1.87 0.79 0.77 ns ? 1.7~1.9v 20pf 1.28 1.30 0.53 0.54 ? 1.7~1.9v 50pf 0.62 0.72 0.26 0.30 ? 3.0~3.6v 10pf 3.04 3.18 1.22 1.34 ? 3.0~3.6v 20pf 2.12 2.08 0.85 0.90 ? 3.0~3.6v 50pf 1.09 1.03 0.45 0.45 ? output pad slew rate (medium drive) tps 1.7~1.9v 10pf 1.50 1.50 0.61 0.63 ns ? 1.7~1.9v 20pf 0.93 1.01 0.39 0.43 ? 1.7~1.9v 50pf 0.43 0.52 0.18 0.22 ? 3.0~3.6v 10pf 2.40 2.45 0.98 1.06 ? 3.0~3.6v 20pf 1.59 1.54 0.65 0.67 ? 3.0~3.6v 50pf 0.76 0.72 0.32 0.32 ?
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 27 table 30 shows the clk-type gpio ac timing and parameters. output pad slew rate (low drive) tps 1.7~1.9v 10pf 1.44 1.51 0.59 0.63 ns ? 1.7~1.9v 20pf 0.84 0.96 0.35 0.40 ? 1.7~1.9v 50pf 0.36 0.46 0.16 0.19 ? 3.0~3.6v 10pf 1.48 1.39 0.59 0.60 ? 3.0~3.6v 20pf 0.88 0.82 0.37 0.36 ? 3.0~3.6v 50pf 0.39 0.36 0.17 0.16 ? input pad average hysteresis tih 1.7 v?1.9 v ? 100 75 mv ? 3.0 v?3.6 v ? 100 50 ? table 30. clk-type gpio parameters symbol test voltage test capacita nce min rise/fall max rise/fall units notes duty cycle fduty ? ? ? ? % ? output pad transition times (maximum drive) tpr 1.7~1.9v 10pf 0.48 0.52 1.08 1.12 ns ? 1.7~1.9v 20pf 0.72 0.74 1.56 1.56 ? 1.7~1.9v 50pf 1.41 1.28 3.04 2.7 ? 3.0~3.6v 10pf 0.61 0.57 1.25 1.12 ? 3.0~3.6v 20pf 0.85 0.85 1.73 1.63 ? 3.0~3.6v 50pf 1.56 1.63 3.13 3.08 ? output pad transition times (medium drive) tpr 1.7~1.9v 10pf 0.76 0.76 1.67 1.62 ns ? 1.7~1.9v 20pf 1.22 1.14 2.64 2.41 ? 1.7~1.9v 50pf 2.66 2.2 5.61 4.62 ? 3.0~3.6v 10pf 0.9 0.89 1.83 1.72 ? 3.0~3.6v 20pf 1.37 1.41 2.77 2.69 ? 3.0~3.6v 50pf 2.85 3.03 5.59 5.72 ? output pad slew rate (maximum drive) tps 1.7~1.9v 10pf 2.38 2.19 0.94 0.91 ns ? 1.7~1.9v 20pf 1.58 1.54 0.65 0.65 ? 1.7~1.9v 50pf 0.81 0.89 0.34 0.38 ? 3.0~3.6v 10pf 3.54 3.79 1.44 1.61 ? 3.0~3.6v 20pf 2.54 2.54 1.04 1.10 ? 3.0~3.6v 50pf 1.38 1.33 0.58 0.58 ? table 29. f-type gpio (continued) parameters symbol test voltage test capaci tance min rise/fall max rise/fall units notes
i.mx28 applications processors data sh eet for consumer products, rev. 1 28 freescale semiconductor 3.5 module timing and electrical parameters 3.5.1 adc electrical specifications this section describes the electri cal specifications, including dc and ac information, of low-resolution adc (lradc) and high-speed adc (hsadc). 3.5.1.1 lradc electrical specifications table 31 shows the electrical speci fications for the lradc. output pad slew rate (medium drive) tps 1.7~1.9v 10pf 1.50 1.50 0.61 0.63 ns ? 1.7~1.9v 20pf 0.93 1.00 0.39 0.42 ? 1.7~1.9v 50pf 0.43 0.52 0.18 0.22 ? 3.0~3.6v 10pf 2.40 2.43 0.98 1.05 ? 3.0~3.6v 20pf 1.58 1.53 0.65 0.67 ? 3.0~3.6v 50pf 0.76 0.71 0.32 0.31 ? input pad average hysteresis tih 1.7 v?1.9 v ? 100 75 mv ? 3.0 v?3.6 v ? 100 50 ? table 31. lradc electrical specifications parameter conditions min. typ. max. unit ac electrical specification input capacitance ( c p ) no pin/pad capacitance included ? 0.5 ? pf resolution ? 12 bits maximum sampling rate 1 (fs) 1 there is no sample and hold circuit in lradc, so it is only for dc input voltage or ones with very small slope. ? ? ? 428 khz power-up time 2 ? 1 sample cycles dc electrical specification dc input voltage 0 1.85 v current consumption 3 vdda vddd ??tbd?ma ma touchscreen interface expected plate resistance ? 200 ? 50000 table 30. clk-type gpio (continued) parameters symbol test voltage test capacita nce min rise/fall max rise/fall units notes
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 29 3.5.1.2 hsadc electrical specification table 32 shows the electrical speci fications for the hsadc 3.5.2 dpll electrical specifications this section includes descriptions of the usb pll electrical specifications a nd ethernet pll electrical specifications. 3.5.2.1 usb pll electrical specifications the i.mx28 integrates a high-frequency usb pll that provides the 480-mhz cloc k for the usb and other system blocks. table 33 lists the usb pll output electrical specifications. 2 this comprises only the required initial dummy conversion cycle, not including the analog part power-up time. 3 this value only includes the adc and the driver switches, but it does not take into account the current consumption in the touchscreen plate. for example, if the plate resistance is 200 ohm, the total current consumption is about 11 ma. table 32. hsadc electrical specification parameter conditions min. typ. max. unit ac electrical specification input sampling capacitance (c s ) no pin/pad capacitance included ? 0.5 ? pf resolution ? 12 bits maximum sampling rate (fs) ???2mhz power-up time ? 1 sample cycles dc electrical specification dc input voltage ? 0.5 ? vdda-0.5 v current consumption vdda vddd ??tbd?ma ma dnl fin = 1 khz ? ? tbd lsb inl fin = 1khz ? ? tbd lsb table 33. usb pll specifications parameter test conditions min typ max unit pll lock time ? ? ? 10 s
i.mx28 applications processors data sh eet for consumer products, rev. 1 30 freescale semiconductor 3.5.2.2 ethernet pll electrical specifications i.mx28 provides a 50-mhz/25-mhz output cl ock, called the ethernet pll output. table 34 lists the ethernet pll out put electrical specifications. table 34. ethernet pll specifications parameter test conditions min typ max unit output duty cycle ? 45 50 55 % pll lock time ? ? ? 10 s cycle to cycle jitter ? ? 25 ? ps clock output frequency tolerance 1 1 this ethernet output clock tolerance sp ecification is the contribution from t he pll only and assumes a perfect 24 mhz clock/crystal source with 0 ppm deviation. the 24 mhz crystal frequency tolerance/deviation should be added to this number for the total ethernet clock output frequency tolerance. ???+/-20ppm
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 31 3.5.3 emi ac timing this section includes descriptions of the electrical specif ications of emi module wh ich interfaces external ddr2 and mobile-ddr1 (lp- ddr1) memory devices. 3.5.3.1 emi command & address ac timing figure 5 and table 35 specify the timing related to the addres s and command pins that interfaces ddr2 and mobile-ddr1 memory devices. figure 5. emi command/address ac timing table 35. emi command/address ac timing id description symbol min. max. unit ddr1 ck cycle time tck 4.86 ? ns ddr2 ck high level width tch 0.5 tck ?0.5 0.5 tck + 0.5 ns emi_clk emi_clkn emi_ce0n emi_rasn emi_casn emi_wen bank row bank column emi_addr ddr1 ddr2 ddr3 ddr4 ddr5 ddr4 ddr5 ddr4 ddr5
i.mx28 applications processors data sh eet for consumer products, rev. 1 32 freescale semiconductor 3.5.3.2 ddr output ac timing figure 6 and table 36 show the ddr output ac timing defined for all ddr types: lpddr1, standard ddr2 (1.8 v), and lvddr2 (1.5 v) figure 6. ddr output ac timing ddr3 ck low level width tcl 0.5 tck ?0.5 0.5 tck + 0.5 ns ddr4 address and control output setup time tis 0.5 tck ? 1 0.5 tck + 0.5 ns ddr5 address and control output hold time tih 0.5 tck ? 1 0.5 tck + 0.5 ns table 36. ddr output ac timing id description symbol min max unit ddr10 positive dqs latching edge to associated ck edge tdqss ?0.5 0.5 ns ddr11 dqs falling edge from ck rising edge?hold time tdsh 0.5 tck ?0.5 0.5 tck + 0.5 ns ddr12 dqs falling edge to ck rising edge?setup time tdss 0.5 tck ?0.5 0.5 tck + 0.5 ns table 35. emi command/address ac timing (continued) id description symbol min. max. unit emi_clk emi_clkn emi_dqs ddr13 ddr14 d0 ddr10 d1 d2 d3 emi_dq & emi_dqm ddr11 ddr12 ddr15 ddr16 emi_dqsn
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 33 3.5.3.3 ddr2 input ac timing figure 7 and table 37 show input ac timing for standard ddr2 and lvddr2. figure 7. ddr2 input ac timing ddr13 dqs output high pulse width tdqsh 0.5 tck ?0.5 0.5 tck + 0.5 ns ddr14 dqs output low pulse width tdqsl 0.5 tck ?0.5 0.5 tck + 0.5 ns ddr15 dq & dqm output setup time relative to dqs tds 1/4 tck ?0.8 1/4 tck ?0.5 ns ddr16 dq & dqm output hold time relative to dqs tdh 1/4 tck ?0.8 1/4 tck ?0.5 ns table 37. ddr2 input ac timing id description symbol min max unit ddr20 positive dqs latching edge to associated ck edge tdqsck ?0.5 0.5 ns ddr21 dqs to dq input skew tdqsq 0.25 tck ?0.85 0.25 tck ?0.5 ns ddr22 dqs to dq input hold time tqh 0.25 tck +0.75 0.25 tck + 1 ns table 36. ddr output ac timing (continued) id description symbol min max unit emi_clk emi_clkn emi_dqs ddr21 ddr22 d0 ddr20 d1 d2 d3 emi_dq emi_dqsn
i.mx28 applications processors data sh eet for consumer products, rev. 1 34 freescale semiconductor 3.5.3.4 lpddr1 input ac timing figure 8 and table 38 show input ac timing for lpddr1. figure 8. lpddr1 input ac timing 3.5.4 ethernet mac controller (enet) timing the enet is designed to support bot h 10- and 100-mbps ethernet netw orks compliant with ieee 802.3. an external transceiver interface and transceiver f unction are required to complete the interface to the media. the enet supports 10/100-mbps mii (18 pins al together), 10/100-mbps rmii (10 pins, including serial management interface), for connection to an external ethernet transceiver. all signals are compatible with transceivers operating at a voltage of 3.3 v. the following subsections describe the timing for mii and rmii modes. table 38. ddr2 input ac timing id description symbol min max unit ddr20 positive dqs latching edge to associated ck edge tdqsck 2 6 ns ddr21 dqs to dq input skew tdqsq 0.25 tck ?0.85 0.25 tck ?0.5 ns ddr22 dqs to dq input hold time tqh 0.25 tck +0.75 0.25 tck + 1 ns emi_clk emi_clkn emi_dqs ddr21 ddr22 d0 ddr20 d1 d2 d3 emi_dq emi_dqsn
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 35 3.5.4.1 enet mii mode timing this subsection describes mii receive, transmit, as ynchronous inputs, and serial management signal timings. 3.5.4.1.1 mii receive sig nal timing (enet0_rxd[3:0], enet0_rx_dv, enet0_rx_er, and enet0_rx_clk) the receiver functions correctl y up to an enet0_rx_clk maximu m frequency of 25 mhz + 1%. there is no minimum frequency requirement. additionally, the processor clock frequency must exceed twice the enet0_rx_clk frequency. figure 9 shows mii receiv e signal timings. table 39 describes the timing para meters (m1?m4) shown in the figure. figure 9. mii receive signal timing diagram 1 enet0_rx_dv, enet0_rx_clk, and enet0_rxd0 have the same timing in 10 mbps 7-wire interface mode. 3.5.4.1.2 mii transmit signal timi ng (enet0_txd[3:0] , enet0_tx_en, enet0_tx_er, and enet0_tx_clk) the transmitter functions correctly up to an enet0_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requi rement. additionally, the processo r clock frequency must exceed twice the enet0_tx_clk frequency. table 39. mii receive signal timing id characteristic 1 min. max. unit m1 enet0_rxd[3:0], enet0_rx_dv, enet0_rx_er to enet0_rx_clk setup 5? ns m2 enet0_rx_clk to enet0_r xd[3:0], enet0_rx_dv, enet0_rx_er hold 5? ns m3 enet0_rx_clk pulse width high 35% 65% enet0_rx_clk period m4 enet0_rx_clk pulse width low 35% 65% enet0_rx_clk period enet0_rx_clk (input) enet0_rxd[3:0] (inputs) enet0_rx_dv enet0_rx_er m3 m4 m1 m2
i.mx28 applications processors data sh eet for consumer products, rev. 1 36 freescale semiconductor figure 10 shows mii transm it signal timings. table 40 describes the timing pa rameters (m5?m8) shown in the figure. figure 10. mii transmit signal timing diagram 1 enet0_tx_en, enet0_tx_clk, and enet0_txd0 have the same timing in 10-mbps 7-wire interface mode. 3.5.4.1.3 mii asynchronous inputs signal timing (e net0_crs and enet0_col) figure 11 shows mii asynchronous input timings. table 41 describes the timing pa rameter (m9) shown in the figure. figure 11. mii async inputs timing diagram 1 enet0_col has the same timing in 10-mbit 7-wire interface mode. table 40. mii transmit signal timing id characteristic 1 min. max. unit m5 enet0_tx_clk to enet0_ txd[3:0], enet0_tx_en, enet0_tx_er invalid 5? ns m6 enet0_tx_clk to enet0_ txd[3:0], enet0_tx_en, enet0_tx_er valid ?20 ns m7 enet0_tx_clk pulse width high 35% 65% enet0_tx_clk period m8 enet0_tx_clk pulse width low 35% 65% enet0_tx_clk period table 41. mii asynchronous inputs signal timing id characteristic min. max. unit m9 1 enet0_crs to enet0_col minimum pulse width 1.5 ? enet0_tx_clk period enet0_tx_clk (input) enet0_txd[3:0] (outputs) enet0_tx_en enet0_tx_er m7 m8 m5 m6 enet0_crs, enet0_col m9
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 37 3.5.4.1.4 mii serial m anagement channel timing (e net0_mdio and enet0_mdc) the mdc frequency is designed to be equal to or less than 2.5 mhz to be compatible with the ieee 802.3 mii specification. however the enet can function correctly with a maximum mdc frequency of 15 mhz. figure 12 shows mii asynchronous input timings. table 42 describes the timing parameters (m10?m15) shown in the figure. figure 12. mii serial management channel timing diagram 3.5.4.2 rmii mode timing in rmii mode, enet_clk is used as the ref_cl k, which is a 50 mhz 50 ppm continuous reference clock. enet0_rx_dv is used as the crs_dv in rmii. other signals unde r rmii mode include enet0_tx_en, enet0_txd[1:0], enet0_rxd[1:0] and enet0_rx_er. table 42. mii serial management channel timing id characteristic min. max. unit m10 enet0_mdc falling edge to enet0_mdio output invalid (min. propagation delay) 0? ns m11 enet0_mdc falling edge to enet0_mdio output valid (max. propagation delay) ?5 ns m12 enet0_mdio (input) to enet0_mdc rising edge setup 18 ? ns m13 enet0_mdio (input) to enet0_mdc rising edge hold 0 ? ns m14 enet0_mdc pulse width high 40% 60% enet0_mdc period m15 enet0_mdc pulse width low 40% 60% enet0_mdc period enet0_mdc (output) enet0_mdio (output) m14 m15 m10 m11 m12 m13 enet0_mdio (input)
i.mx28 applications processors data sh eet for consumer products, rev. 1 38 freescale semiconductor figure 13 shows rmii mode timings. table 43 describes the timing parame ters (m16?m21) shown in the figure. figure 13. rmii mode signal timing diagram 3.5.5 coresight etm9 ac interface timing the following timing specifications are given as a guide for a tpa th at supports traceclk frequencies up to 80 mhz. 3.5.5.1 traceclk timing this section describes traceclk timings. table 43. rmii signal timing id characteristic min. max. unit m16 enet_clk pulse width high 35% 65% enet_clk period m17 enet_clk pulse width low 35% 65% enet_clk period m18 enet_clk to enet0_txd[1:0 ], enet0_tx_en invalid 3 ? ns m19 enet_clk to enet0_txd[1:0 ], enet0_tx_en valid ? 12 ns m20 enet0_rxd[1:0], crs_dv(enet0_rx_dv), enet0_rx_er to enet_clk setup 2? ns m21 enet_clk to enet0_rxd[1:0], en et0_rx_dv, enet0_rx_er hold 2 ? ns enet_clk (input) enet0_tx_en m16 m17 m18 m19 m20 m21 enet0_rxd[1:0] enet0_txd[1:0] (output) enet0_rx_er crs_dv (input)
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 39 figure 14 shows traceclk signal timings. table 44 describes the timing parameters shown in the figure. figure 14. traceclk signal timing diagram 3.5.5.2 trace data signal timing figure 15 shows the setup and hold require ments of the trace data pins with respect to traceclk. table 45 describes the timing parameters shown in the figure. figure 15. mii transmit signal timing diagram table 44. mii receive signal timing id characteristic 1 min. max. unit tr clock and data raise time 3 ? ns tf clock and data fall time 3 ? ns twh high pulse wide 2 ? ns twl low pulse wide 2 ? ns tcyc clock period 12.5 ? ns table 45. mii transmit signal timing id characteristic 1 min. max. unit ts data setup 2 ? ns th data hold 2 ? ns
i.mx28 applications processors data sh eet for consumer products, rev. 1 40 freescale semiconductor 3.5.6 flexcan ac timing table 46 and table 47 show voltage requirements for the fl excan transceiver tx and rx pins. figure 16 through figure 19 show the flexcan timing, including timing of the standby and shutdown signals. figure 16. flexcan timing diagram table 46. tx pin characteristics parameter symbol min. typ. max. units high-level output voltage v oh 2? vcc 1 + 0.3 1 vcc = +3.3 v 5% v low-level output voltage v ol ?0.8 ? v table 47. rx pin characteristics parameter symbol min. typ. max. units high-level input voltage v ih 0.8 vcc 1 1 vcc = +3.3 v 5% ? vcc 1 v low-level input voltage v il ?0.4 ? v txd v diff rxd v cc /2 t ontxd t offtxd t onrxd t offrxd v cc /2 v cc /2 0.5v 0.9v v cc /2
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 41 figure 17. timing diagram for flexcan standby signal figure 18. timing diagram for flexcan shutdown signal figure 19. timing diagram for flexcan shutdown-to-standby signal rs v diff rxd v cc /2 v cc /2 t sbrxdl t drxdl 1.1v v cc x 0.75 bus externally driven shdn v diff rxd v cc /2 v cc /2 bus externally driven t offshdn t onshdn v cc /2 0.5v shdn rs v cc /2 0.75 x v cc t shdnsb
i.mx28 applications processors data sh eet for consumer products, rev. 1 42 freescale semiconductor 3.5.7 general-purpose media interface (gpmi) timing the i.mx28 gpmi controller is a flexible interface nand flash controller with 8-bit data width, up to 50mb/s i/o speed and i ndividual chip select. it supports normal timing mode, using two flash clock cycles for one access of re and we . ac timings are provided as multiplications of the clock cycle and fixed delay. figure 20 , figure 21 , figure 22 and figure 23 depict the relative timing be tween gpmi signals at the module level for different operations under normal mode. table 48 describes the timing parameters (nf 1?nf17) that are shown in the figures. figure 20. command latch cycle timing diagram figure 21. address latch cycle timing diagram cle cen we ale io[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nf6 nf7 cle cen we ale io[7:0] address nf9 nf8 nf1 nf5 nf3 nf4 nf6 nf11 nf10 nf7
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 43 figure 22. write data latch cycle timing diagram figure 23. read data latch cycle timing diagram cle cen we ale io[7:0] data to nf nf9 nf8 nf1 nf5 nf3 nf6 nf11 nf10 nf7 cle cen re rb io[7:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16
i.mx28 applications processors data sh eet for consumer products, rev. 1 44 freescale semiconductor table 48. nfc timing parameters 1 1 the flash clock maximum frequency is 100 mhz. 2)gpmi?s output timing could be controlled by module?s internal register, say hw_gpmi_timing0_address_set up,hw_gpmi_timing0_data_setup,hw_gp mi_timing0_data_hold, this ac timing depends on these registers? setting. in the above table we use as/ds/dh repr esenting these settings each. 3)as minimum value could be 0, while ds/dh minimum value is 1. id parameter symbol timing t = gpmi clock cycle example timing for gpmi clock 100 mhz t = 10ns unit min. max. min. max. nf1 cle setup time tcls (as+1)*t ? 10 ? ns nf2 cle hold time tclh (dh+1)*t ? 20 ? ns nf3 cen setup time tcs (as+1)*t ? 10 ? ns nf4 ce hold time tch (dh+1)*t ? 20 ? ns nf5 we pulse width twp ds*t 10 ns nf6 ale setup time tals (as+1)*t ? 10 ? ns nf7 ale hold time talh (dh+1)*t ? 20 ? ns nf8 data setup time tds ds*t ? 10 ? ns nf9 data hold time tdh dh*t ? 10 ? ns nf10 write cycle time twc (ds+dh)*t 20 ns nf11 we hold time twh dh*t 10 ns nf12 ready to re low trr (as+1)*t ? 10 ? ns nf13 re pulse width trp ds*t ? 10 ? ns nf14 read cycle time trc (ds+dh)*t ? 20 ? ns nf15 re high hold time treh dh*t 10 ? ns nf16 data setup on read tdsr n/a 10 ? ns nf17 data hold on read tdhr n/a 10 ? ns
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 45 3.5.8 lcd ac output electrical specifications figure 24 depicts the ac output timing for the lcd module. table 49 lists the lcd module timing parameters. figure 24. lcd ac output timing diagram table 49. lcd ac output timing parameters id parameter description tsf data setup for falling edge dotck = t/2 ? 1.97ns + 0.15*cck ? 0.19*cd thf data hold for falling edge dotck = t/2 + 0.29ns + 0.09*cd ? 0.10*cck tsr data setup for rising edge dotck = t/2 ? 2.09ns + 0.18*cck ? 0.19*cd thr data hold for rising edge dotck = t/2 + 0.40ns + 0.09*cd ? 0.10*cck tdw data valid window tdw = t ? 1.45ns pad_lcd_dotck falling edge capture notes: t = lcd interface clock period i/o drive strength = 4ma i/o voltage = 3.3v cck = capacitance load on dotck pad cd = capacitance load on data/ctrl pad pad_lcd_d[17:0], pad_lcd_vsync, etc data/ctrl tdw tsf thf pad_lcd_dotck rising edge capture tsr thr t
i.mx28 applications processors data sh eet for consumer products, rev. 1 46 freescale semiconductor 3.5.9 inter ic (i 2 c) timing the i 2 c module is designed to support up to 400-kbps i 2 c connection compliant with i 2 c bus protocol. the following section describes i 2 c sda and scl signal timings. figure 25 shows the timing of the i 2 c module. table 50 describes the i 2 c module timing parameters (ic1?ic11) shown in the figure. figure 25. i 2 c module timing diagram table 50. i 2 c module timing pa rameters: 1.8 v ? 3.6 v id parameter standard mode fast mode unit min. max. min. max. ic1 i2c_scl cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 n s for the i2c_sda signal in order to bridge the undefined region of the falling edge of i2c_scl. 3.45 2 2 the maximum ic4 has to be met only if the device does not stretch the low period (id no ic5) of the i2c_scl signal. 0 1 0.9 2 s ic5 high period of i2c_scl clock 4.0 ? 0.6 ? s ic6 low period of the i2c_scl clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i2c bus device can be used in a standard-mode i 2 c bus system, but the requirement of set-up time (id no ic7) of 250 ns must then be met. this is automatically the case if t he device does not stretch the low period of the i2c_scl signal. if such a device does stretch the low period of the i2c_scl si gnal, it must output the next data bit to the i2c_sda line max_rise_time (id no ic9) + data_setup _time (id no ic7) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the i2c_scl line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2c_sda and i2c_scl signals ? 1000 20+0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both i2c_sda and i2c_scl signals ? 300 20+0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2c_sda i2c_scl ic1
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 47 3.5.10 jtag interface timing figure 26 through figure 29 show respectively the test clock i nput, boundary scan, test access port, and trst timings for the sjc. table 51 describes the sjc timing paramete rs (sj1?sj13) indicated in the figures. figure 26. test clock input timing diagram figure 27. boundary scan (jtag) timing diagram tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3 tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6
i.mx28 applications processors data sh eet for consumer products, rev. 1 48 freescale semiconductor figure 28. test access port timing diagram figure 29. trst timing diagram table 51. sjc timing parameters id parameter all frequencies unit min. max. sj1 tck cycle time 100 ? ns sj2 tck clock pulse width measured at v m 1 40 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 10 ? ns sj5 boundary scan input data hold time 50 ? ns sj6 tck low to output data valid ? 50 ns sj7 tck low to output high impedance ? 50 ns sj8 tms, tdi data set-up time 10 ? ns sj9 tms, tdi data hold time 50 ? ns tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10 tck (input) trst (input) sj13 sj12
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 49 3.5.11 pulse width modulator (pwm) timing figure 30 depicts the timing of the pwm, and table 52 lists the pwm timi ng characteristics. the pwm can be programmed to select one of two clock signals as its source frequency: xtal clock or hsadc clock. the selected clock si gnal is passed through a prescaler befo re being input to the counter. the output is available at the pulse width modulator output (pwmo) external pin. pwm also supports matt mode. in this mode, it can be programmed to select one of two clock signals as its source frequency, 24-mhz or 32-khz crystal clock. for a 32- khz source cloc k input, the pwm outputs the 32-khz clock directly to pad. figure 30. pwm timing sj10 tck low to tdo data valid ? 44 ns sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns 1 v m ? mid point voltage table 52. pwm output timing parameter: xtal clock ref no. parameter minimum maximum unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 0 24mhz mhz 2a clock high time 21 ? ns 2b clock low time 21 ? ns 3a clock fall time ? 0.3 ns 3b clock rise time ? 0.3 ns 4a output delay time ? 15.08 ns 4b output setup time 15.77 ? ns table 51. sjc timing parameters (continued) id parameter all frequencies unit min. max. 4a pwm source clock 2a 1 pwm output 2b 3a 3b 4b
i.mx28 applications processors data sh eet for consumer products, rev. 1 50 freescale semiconductor figure 31. pwm timing figure 32. pwm timing table 53. pwm output timing parameter: hsadc clock ref no. parameter minimum maximum unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 032mhz 2a clock high time 6.813 ? ns 2b clock low time 24.432 ? ns 3a clock fall time ? 0.3 ns 3b clock rise time ? 0.3 ns 4a output delay time ? 14.93 ns 4b output setup time 15.71 ? ns 4a pwm source clock 2a 1 pwm output 2b 3a 3b 4b pwm source clock pwm output 2a 4a 3a 2b 3b 4b
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 51 3.5.12 serial audio interface (saif) ac timing the following subsections descri be saif timing in two cases: ? transmitter ? receiver 3.5.12.1 saif transmitter timing figure 33 shows the timing for saif trans mitter with internal clock, and table 55 describes the timing parameters (ss1?ss13). figure 33. saif transmitter timing diagram table 54. pwm output timing parameter: matt mode 24 mhz crystal clock ref no. parameter minimum maximum unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 24 24 mhz 2a clock high time 20.99 ? ns 2b clock low time 21.01 ? ns 3a clock fall time ? 0.3 ns 3b clock rise time ? 0.3 ns 4a output delay time ? 15.23 ns 4b output setup time 15.92 ? ns bitclk lrclk ss1 sdata0-2 ss2 ss4 ss3 ss5 ss6 ss7 ss8 ss9 ss12 ss13 ss10 ss11
i.mx28 applications processors data sh eet for consumer products, rev. 1 52 freescale semiconductor 3.5.12.1.5 saif receiver timing figure 34 shows the timing for the saif receiver with internal clock. table 56 describes the timing parameters (ss1?ss17) shown in the figure. figure 34. saif recei ver timing diagram table 55. saif transmitter timing id parameter min. max. unit ss1 bitclk period 81.4 ? ns ss2 bitclk high period 36.0 ? ns ss3 bitclk rise time ? 6.0 ns ss4 bitclk low period 36.0 ? ns ss5 bitclk fall time ? 6.0 ns ss6 bitclk high to lrclk high ? 15.0 ns ss7 bitclk high to lrclk low ? 15.0 ns ss8 lrclk rise time ? 6.0 ns ss9 lrclk fall time ? 6.0 ns ss10 bitclk high to sdata valid from high impedance ? 15.0 ns ss11 bitclk high to sdata high/low ? 15.0 ns ss12 bitclk high to sdata high impedance ? 15.0 ns ss13 sdata rise/fall time ? 6.0 ns bitclk lrclk sdata0-2 ss1 ss4 ss2 ss16 ss17 ss14 ss15 ss3 ss5
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 53 3.5.13 spdif ac timing spdif data is sent using bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bi t rate of the data signal. the following table 57 shows spdif timing parameters, including the timing of the modulating tx clock (spdif_clk) in spdif transmitter as shown in the figure 35 . figure 35. spdif_clk timing table 56. saif receiver timing with internal clock id parameter min. max. unit ss1 bitclk period 81.4 ? ns ss2 bitclk high period 36.0 ? ns ss3 bitclk rise time ? 6.0 ns ss4 bitclk low period 36.0 ? ns ss5 bitclk fall time ? 6.0 ns ss14 bitclk high to lrclk high ? 15.0 ns ss15 bitclk high to lrclk low ? 15.0 ns ss16 sdata setup time before bitclk high 10.0 ? ns ss17 sdata hold time after bitclk high 0.0 ? ns table 57. spdif timing characteristics symbol timing parameter range unit min max spdifout output (load = 30pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns modulating tx clock (spdif_clk) period spclkp 81.4 ? ns spdif_clk high period spclkph 65.1 ? ns spdif_clk low period spclkpl 65.1 ? ns spdif_clk (input) spclkp spclkph spclkpl
i.mx28 applications processors data sh eet for consumer products, rev. 1 54 freescale semiconductor 3.5.14 synchronous serial port (ssp) ac timing this section describes the electrical informati on of the ssp, which includes sd/mmc4.3 (single data rate) timing, mmc4.4 (dual date rate) timi ng, ms (memory stick) timing, and spi timing. 3.5.14.1 sd/mmc4.3 (single data rate) ac timing figure 36 depicts the timing of sd/mmc4.3, and table 58 lists the sd/mmc4.3 ti ming characteristics. figure 36. sd/mmc4.3 timing table 58. sd/mmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 025/50mhz clock frequency (mmc full speed/high speed) f pp 3 020/52mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns ssp output / card inputs cmd, dat (reference to clk) sd6 ssp output delay t od -5 5 ns ssp input / card outputs cmd, dat (reference to clk) sd1 sd3 sd5 sd4 sd7 cmd output from ssp to card dat1 ...... dat7 dat0 cmd input from card to ssp dat1 ...... dat7 dat0 sck sd2 sd8 sd6
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 55 3.5.14.2 mmc4.4 (dual data rate) ac timing figure 37 depicts the timing of mmc4.4, and table 59 lists the mmc4.4 timing ch aracteristics. be aware that only data0?data7 are sampled on both edge s of the clock (not applicable to cmd). figure 37. mmc4.4 timing sd7 ssp input setup time t isu 2.5 ? ns sd8 ssp input hold time t ih 4 2.5 ? ns 1 in low speed mode, the card clock must be lower than 400 khz, and the voltage r anges from 2.7 to 3.6 v. 2 in normal speed mode for the sd/sdio card, clock frequency can be any value between 0 ~ 25 mhz. in high speed mode, clock frequency can be any value between 0 ~ 50 mhz. 3 in normal speed mode for mmc card, clock frequency can be any value between 0 ~ 20 mhz. in high speed mode, clock frequency can be any value between 0 ~ 52mhz. 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns. table 59. mmc4.4 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (mmc full speed/high speed) f pp 052mhz ssp output / card inputs cmd, dat (reference to clk) sd2 ssp output delay t od ?5 5 ns ssp input / card outputs cmd, dat (reference to clk) sd3 ssp input setup time t isu 2.5 ? ns sd4 ssp input hold time t ih 2.5 ? ns table 58. sd/mmc4.3 interface timing specification (continued) id parameter symbols min max unit sd1 sd2 sd3 output from ssp to card dat1 ...... dat7 dat0 input from card to ssp dat1 ...... dat7 dat0 sck sd4 sd2 ...... ......
i.mx28 applications processors data sh eet for consumer products, rev. 1 56 freescale semiconductor 3.5.14.3 ms (memory stick) ac timing the ssp module, which also has the function of a memo ry stick host controller, is compatible with the sony memory stick version 1.x and memory stick pro. figure 38 , figure 39 and table 40 show the timing of the memory stick. table 60 and table 61 list the memory stick timing characteristics. figure 38. ms clock time waveforms figure 39. ms serial transfer mode timing diagram 20% 80% 80% 20% sck 50% 50% 20% 80% 50% ms4 ms2 ms5 ms3 ms1 sck bs(cmd) data (output) data (input) ms1 ms6 ms7 ms8 ms9 ms10
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 57 figure 40. ms parallel transfer mode timing diagram table 60. ms serial transfer timing parameters id parameter symbol min max units ms1 sck cycle time tclkc 50 ? ns ms2 sck high pulse time tclkwh 15 ? ns ms3 sck low pulse time tclkwl 15 ? ns ms4 sck rise time tclkr ? 10 ns ms5 sck fall time tclkf ? 10 ns ms6 bs setup time tbssu 5 ? ns ms7 bs hold time tbsh 5 ? ns ms8 data setup time tdsu 5 ? ns ms9 data hold time tdh 5 ? ns ms10 data input delay time tdd ? 15 ns table 61. ms parallel transfer timing parameters id parameter symbol min max units ms1 sck cycle time tclkc 25 ? ns ms2 sck high pulse time tclkwh 5 ? ns ms3 sck low pulse time tclkwl 5 ? ns sck bs(cmd) data (output) data (input) ms1 ms11 ms12 ms13 ms14 ms15
i.mx28 applications processors data sh eet for consumer products, rev. 1 58 freescale semiconductor 3.5.14.4 spi ac timing figure 41 depicts the master mode and slav e mode timings of the spi, and table 62 lists the timing parameters. figure 41. spi interface timing diagram ms4 sck rise time tclkr ? 10 ns ms5 sck fall time tclkf ? 10 ns ms11 bs setup time tbssu 8 ? ns ms12 bs hold time tbsh 1 ? ns ms13 data setup time tdsu 8 ? ns ms14 data hold time tdh 1 ? ns ms15 data input delay time tdd ? 15 ns table 62. spi interface timing parameters id parameter symbol min. max. units cs1 sck cycle time t clk 50 ? ns cs2 sck high or low time t sw 25 ? ns cs3 sck rise or fall t rise/fall ?7.6ns cs4 ss n pulse width t cslh 25 ? ns cs5 ss n lead time (cs setup time) t scs 25 ? ns cs6 ss n lag time (cs hold time) t hcs 25 ? ns cs7 mosi setup time t smosi 5?ns cs8 mosi hold time t hmosi 5?ns cs9 miso setup time t smiso 5?ns cs10 miso hold time t hmiso 5?ns table 61. ms parallel transfer timing parameters (continued) id parameter symbol min max units cs7 cs8 cs2 cs2 cs4 cs6 cs9 cs10 sck ss n miso mosi cs1 cs3 cs3 cs5
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 59 3.5.15 uart (uartapp and debuguart) ac timing this section describes the uart module ac timi ng which is applicable to both uartapp and debuguart. 3.5.15.1 uart transmit timing figure 39 shows the uart transmit timing, showing only eight data bits and one stop bit. table 63 describes the timing paramete r (ua1) shown in the figure. figure 42. uart transmit timing diagram 3.5.15.2 uart receive timing figure 43 shows the uart receive timing, showing onl y eight data bits and one stop bit. table 64 describes the timing paramete r (ua2) shown in the figure. ? figure 43. uart receive timing diagram table 63. uart transmit timing parameters id parameter symbol min. max. units ua1 transmit bit time t tbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uartapp can support is 3.25 mbps. the maximum baud rate of debuguart is 115.2 kbps. 2 t ref_clk : the period of uart reference clock ref_clk (which is apbx clock = 24 mhz). 1/f baud_rate + t ref_clk ? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2
i.mx28 applications processors data sh eet for consumer products, rev. 1 60 freescale semiconductor 4 package information and contact assignments 4.1 289-ball mapbga?case 14 x 14 mm, 0.8 mm pitch the following notes apply to figure 44 : ? all dimensions are in millimeters. ? dimensioning and toleranc ing per asme y14.5m-1994. ? maximum solder bump diameter measured parallel to datum a. ? datum a, the seating plane, is determined by the spherical crowns of the solder bumps. ? parallelism measurement excludes any eff ect of mark on top surface of package. table 64. uart receive timing parameters id parameter symbol min. max. units ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 f baud_rate ). t rbit 1/f baud_rate 2 ? 1/(16 f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uartapp can support is 3.25 mbps. the maximum baud rate of debuguart is 115 kbps. 1/f baud_rate + 1/(16 f baud_rate ) ?
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 61 figure 44 shows the i.mx28 production package. figure 44. zzxz i.mx28 production package 4.2 ground, power, sense, and reference contact assignments table 65 shows power and ground contact assignments for the mapbga package. table 65. mapbga power and ground contact assignments contact name contact assignment vdda1 c13 vddd g12,g11,f10,f11,k12,f12,g10 vddio18 g8,f9,f8,g9 vddio33 h8,j8,n3,g3,e6,j9,j10,a7,e16 vddio33_emi n17 vddio_emi p11,r13,n13,n15,g17,m12,m10,g13,m11,l13,g15
i.mx28 applications processors data sh eet for consumer products, rev. 1 62 freescale semiconductor 4.3 signal contact assignments table 66 lists the i.mx287 mapbga package signal contact assignments. vddio_emiq k15,j13,r15 vddxtal c12 vss e15,l11,a1,k10,k11,j11,m 14,h11,u1,h9,h12,h3,k 9,c16,l10,h16,j12,h1 0,b7,e5,j15,a9,n4 vssa1 b13 vssa2 b11 vssio_emi f16,r10, h14,m16,f14, l12,p16,u17,t14,p14,r12 table 66. mapbga contact assignments signal name contact assignment signal name contact assignment signal name contact assignment auart0_cts j6 emi_dqs1n j16 lcd_d17 r3 auart0_rts j7 emi_odt0 r17 lcd_d18 u4 auart0_rx g5 emi_odt1 t17 lcd_d19 t4 auart0_tx h5 emi_rasn r16 lcd_d20 r4 auart1_cts k5 emi_vref0 r14 lcd_d21 u5 auart1_rts j5 emi_vref1 k13 lcd_d22 t5 auart1_rx l4 emi_wen t15 lcd_d23 r5 auart1_tx k4 enet0_col j4 lcd_dotclk n1 aua r t 2 _ c t s h 6 e n e t 0 _ c r s j3 lcd_enable n5 auart2_rts h7 enet0_mdc g4 lcd_hsync m1 auart2_rx f6 enet0_mdio h4 lcd_rd_e p4 auart2_tx f5 enet0_rxd0 h 1 l c d _ r e se t m 6 auart3_cts l6 enet0_rxd1 h2 lcd_rs m4 auart3_rts k6 enet0_rxd2 j1 lcd_vsync l1 auart3_rx m5 enet0_rxd3 j2 lcd_wr_rwn k1 auart3_tx l5 enet0_rx_clk f3 lradc0 c15 battery a15 enet0_rx_en e4 lradc1 c9 dcdc_batt b15 enet0_txd0 f1 lradc2 c8 dcdc_gnd a17 enet0_txd1 f2 lradc3 d9 dcdc_ln1 b17 enet0_txd2 g1 lradc4 d13 dcdc_lp a16 enet0_txd3 g2 lradc5 d15 table 65. mapbga power and ground contact assignments (continued) contact name contact assignment
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 63 dcdc_vdda b16 enet0_tx_clk e3 lradc6 c14 dcdc_vddd d17 enet0_tx_en f4 pswitch a11 dcdc_vddio c17 enet_clk e2 pwm0 k7 debug b9 gpmi_ale p6 pwm1 l7 emi_a00 u15 gpmi_ce0n n7 pwm2 k8 emi_a01 u12 gpmi_ce1n n9 pwm3 e9 emi_a02 u14 gpmi_ce2n m7 pwm4 e10 emi_a03 t11 gpmi_ce3n m9 resetn a14 emi_a04 u10 gpmi_cle p7 rtc_xtali d11 emi_a05 r11 gpmi_d00 u8 rtc_xtalo c11 emi_a06 r9 gpmi_d01 t8 saif0_bitclk f7 emi_a07 n11 gpmi_d02 r8 saif0_lrclk g6 emi_a08 u9 gpmi_d03 u7 saif0_mclk g7 emi_a09 p10 gpmi_d04 t7 saif0_sdata0 e7 emi_a10 u13 gpmi_d05 r7 saif1_sdata0 e8 emi_a11 t10 gpmi_d06 u6 spdif d7 emi_a12 u11 gpmi_d07 t6 ssp0_cmd a4 emi_a13 t9 gpmi_rdn r6 ssp0_data0 b6 emi_a14 n10 gpmi_rdy0 n6 ssp0_data1 c6 emi_ba0 t16 gpmi_rdy1 n8 ssp0_data2 d6 emi_ba1 t12 gpmi_rdy2 m8 ssp0_data3 a5 emi_ba2 n12 gpmi_rdy3 l8 ssp0_data4 b5 emi_casn u16 gpmi_resetn l9 ssp0_data5 c5 emi_ce0n p12 gpmi_wrn p8 ssp0_data6 d5 emi_ce1n p9 hsadc0 b14 ssp0_data7 b4 emi_cke t13 i2c0_scl c7 ssp0_detect d10 emi_clk l17 i2c0_sda d8 ssp0_sck a6 emi_clkn l16 jtag_rtck e14 ssp1_cmd c1 emi_d00 n16 jtag_tck e11 ssp1_data0 d1 emi_d01 m13 jtag_tdi e12 ssp1_data3 e1 emi_d02 p15 jtag_tdo e13 ssp1_sck b1 emi_d03 n14 jtag_tms d12 ssp2_miso b3 table 66. mapbga contact assignments (continued) signal name contact assignment signal name contact assignment signal name contact assignment
i.mx28 applications processors data sh eet for consumer products, rev. 1 64 freescale semiconductor emi_d04 p13 jtag_trst d14 ssp2_mosi c3 emi_d05 p17 lcd_cs p5 ssp2_sck a3 emi_d06 l14 lcd_d00 k2 ssp2_ss0 c4 emi_d07 m17 lcd_d01 k3 ssp2_ss1 d3 emi_d08 g16 lcd_d02 l2 ssp2_ss2 d4 emi_d09 h15 lcd_d03 l3 ssp3_miso b2 emi_d10 g14 lcd_d04 m2 ssp3_mosi c2 emi_d11 j14 lcd_d05 m3 ssp3_sck a2 emi_d12 h13 lcd_d06 n2 ssp3_ss0 d2 emi_d13 h17 lcd_d07 p1 testmode c10 emi_d14 f13 lcd_d08 p2 usb0dm a10 emi_d15 f17 lcd_d09 p3 usb0dp b10 emi_ddr_ope n k14 lcd_d10 r1 usb1dm b8 emi_ddr_ope n_fb l15 lcd_d11 r2 usb1dp a8 emi_dqm0 m15 lcd_d12 t1 vdd1p5 d16 emi_dqm1 f15 lcd_d13 t2 vdd4p2 a13 emi_dqs0 k17 lcd_d14 u2 vdd5v e17 emi_dqs0n k16 lcd_d15 u3 xtali a12 emi_dqs1 j17 lcd_d16 t3 xtalo b12 table 66. mapbga contact assignments (continued) signal name contact assignment signal name contact assignment signal name contact assignment
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 65 4.4 i.mx287 ball map figure 45 shows the i.mx287 mapbga ball map. figure 45. 289-pin i.mx287 mapbga ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a vss ssp3 _sck ssp2 _sck ssp0 _cmd ssp0 _dat a3 ssp0 _sck vddi o33 usb1 dp vss usb0 dm pswi tch xtali vdd4 p2 rese tn batt ery dcdc _lp dcdc _gnd a b ssp1 _sck ssp3 _mis o ssp2 _mis o ssp0 _dat a7 ssp0 _dat a4 ssp0 _dat a0 vss usb1 dm debu g usb0 dp vssa 2 xtal o vssa 1 hsad c0 dcdc _bat t dcdc _vdd a dcdc _ln1 b c ssp1 _cmd ssp3 _mos i ssp2 _mos i ssp2 _ss0 ssp0 _dat a5 ssp0 _dat a1 i2c0_ scl lrad c2 lrad c1 test mod e rtc_ xtal o vddx tal vdda 1 lrad c6 lrad c0 vss dcdc _vdd io c d ssp1 _dat a0 ssp3 _ss0 ssp2 _ss1 ssp2 _ss2 ssp0 _dat a6 ssp0 _dat a2 spdi f i2c0_ sda lrad c3 ssp0 _det ect rtc_ xtali jtag _tms lrad c4 jtag _trs t lrad c5 vdd1 p5 dcdc _vdd d d e ssp1 _dat a3 enet _clk enet 0_tx _clk enet 0_rx _en vss vddi o33 saif0 _sda ta0 saif1 _sda ta0 pwm 3 pwm 4 jtag _tck jtag _tdi jtag _tdo jtag _rtc k vss vddi o33 vdd5 v e f enet 0_tx d0 enet 0_tx d1 enet 0_rx _clk enet 0_tx _en auar t2_t x auar t2_r x saif0 _bitc lk vddi o18 vddi o18 vddd vddd vddd emi_ d14 vssi o_em i emi_ dqm1 vssi o_em i emi_ d15 f g enet 0_tx d2 enet 0_tx d3 vddi o33 enet 0_md c auar t0_r x saif0 _lrc lk saif0 _mcl k vddi o18 vddi o18 vddd vddd vddd vddi o_em i emi_ d10 vddi o_em i emi_ d08 vddi o_em i g h enet 0_rx d0 enet 0_rx d1 vss enet 0_md io auar t0_t x auar t2_c ts auar t2_r ts vddi o33 vss vss vss vss emi_ d12 vssi o_em i emi_ d09 vss emi_ d13 h j enet 0_rx d2 enet 0_rx d3 enet 0_cr s enet 0_co l auar t1_r ts auar t0_c ts auar t0_r ts vddi o33 vddi o33 vddi o33 vss vss vddi o_em iq emi_ d11 vss emi_ dqs1 n emi_ dqs1 j k lcd_ wr_ rwn lcd_ d00 lcd_ d01 auar t1_t x auar t1_c ts auar t3_r ts pwm 0 pwm 2 vss vss vss vddd emi_ vref 1 emi_ ddr_ open vddi o_em iq emi_ dqs0 n emi_ dqs0 k l lcd_ vsyn c lcd_ d02 lcd_ d03 auar t1_r x auar t3_t x auar t3_c ts pwm 1 gpmi _rdy 3 gpmi _res etn vss vss vssi o_em i vddi o_em i emi_ d06 emi_ ddr_ open _fb emi_ clkn emi_ clk l m lcd_ hsyn c lcd_ d04 lcd_ d05 lcd_ rs auar t3_r x lcd_ rese t gpmi _ce2 n gpmi _rdy 2 gpmi _ce3 n vddi o_em i vddi o_em i vddi o_em i emi_ d01 vss emi_ dqm0 vssi o_em i emi_ d07 m n lcd_ dotc lk lcd_ d06 vddi o33 vss lcd_ enab le gpmi _rdy 0 gpmi _ce0 n gpmi _rdy 1 gpmi _ce1 n emi_ a14 emi_ a07 emi_ ba2 vddi o_em i emi_ d03 vddi o_em i emi_ d00 vddi o33_ emi n p lcd_ d07 lcd_ d08 lcd_ d09 lcd_ rd_e lcd_ cs gpmi _ale gpmi _cle gpmi _wr n emi_ ce1n emi_ a09 vddi o_em i emi_ ce0n emi_ d04 vssi o_em i emi_ d02 vssi o_em i emi_ d05 p r lcd_ d10 lcd_ d11 lcd_ d17 lcd_ d20 lcd_ d23 gpmi _rdn gpmi _d05 gpmi _d02 emi_ a06 vssi o_em i emi_ a05 vssi o_em i vddi o_em i emi_ vref 0 vddi o_em iq emi_ rasn emi_ odt0 r t lcd_ d12 lcd_ d13 lcd_ d16 lcd_ d19 lcd_ d22 gpmi _d07 gpmi _d04 gpmi _d01 emi_ a13 emi_ a11 emi_ a03 emi_ ba1 emi_ cke vssi o_em i emi_ wen emi_ ba0 emi_ odt1 t u vss lcd_ d14 lcd_ d15 lcd_ d18 lcd_ d21 gpmi _d06 gpmi _d03 gpmi _d00 emi_ a08 emi_ a04 emi_ a12 emi_ a01 emi_ a10 emi_ a02 emi_ a00 emi_ casn vssi o_em i u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
i.mx28 applications processors data sh eet for consumer products, rev. 1 66 freescale semiconductor 4.5 i.mx286 ball map figure 46 shows the i.mx286 mapbga ball map. figure 46. 289-pin i.mx286 mapbga ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a vss nc ssp2 _sck ssp0 _cmd ssp0 _dat a3 ssp0 _sck vddi o33 usb1 dp vss usb0 dm pswi tch xtali vdd4 p2 rese tn batt ery dcdc _lp dcdc _gnd a bncnc ssp2 _mis o ssp0 _dat a7 ssp0 _dat a4 ssp0 _dat a0 vss usb1 dm debu g usb0 dp vssa 2 xtal o vssa 1 hsad c0 dcdc _bat t dcdc _vdd a dcdc _ln1 b cncnc ssp2 _mos i ssp2 _ss0 ssp0 _dat a5 ssp0 _dat a1 i2c0_ scl lrad c2 lrad c1 test mod e rtc_ xtal o vddx tal vdda 1 lrad c6 lrad c0 vss dcdc _vdd io c dncnc ssp2 _ss1 ssp2 _ss2 ssp0 _dat a6 ssp0 _dat a2 spdi f i2c0_ sda lrad c3 ssp0 _det ect rtc_ xtali jtag _tms lrad c4 jtag _trs t lrad c5 vdd1 p5 dcdc _vdd d d enc enet _clk nc enet 0_rx _en vss vddi o33 saif0 _sda ta0 saif1 _sda ta0 pwm 3 pwm 4 jtag _tck jtag _tdi jtag _tdo jtag _rtc k vss vddi o33 vdd5 v e f enet 0_tx d0 enet 0_tx d1 nc enet 0_tx _en nc nc saif0 _bitc lk vddi o18 vddi o18 vddd vddd vddd emi_ d14 vssi o_em i emi_ dqm1 vssi o_em i emi_ d15 f gncnc vddi o33 enet 0_md c auar t0_r x saif0 _lrc lk saif0 _mcl k vddi o18 vddi o18 vddd vddd vddd vddi o_em i emi_ d10 vddi o_em i emi_ d08 vddi o_em i g h enet 0_rx d0 enet 0_rx d1 vss enet 0_md io auar t0_t x nc nc vddi o33 vss vss vss vss emi_ d12 vssi o_em i emi_ d09 vss emi_ d13 h j ncncncncnc auar t0_c ts auar t0_r ts vddi o33 vddi o33 vddi o33 vss vss vddi o_em iq emi_ d11 vss emi_ dqs1 n emi_ dqs1 j k lcd_ wr_ rwn lcd_ d00 lcd_ d01 auar t1_t x nc nc pwm 0 pwm 2 vss vss vss vddd emi_ vref 1 emi_ ddr_ open vddi o_em iq emi_ dqs0 n emi_ dqs0 k lnc lcd_ d02 lcd_ d03 auar t1_r x nc nc pwm 1 gpmi _rdy 3 gpmi _res etn vss vss vssi o_em i vddi o_em i emi_ d06 emi_ ddr_ open _fb emi_ clkn emi_ clk l mnc lcd_ d04 lcd_ d05 lcd_ rs nc lcd_ rese t gpmi _ce2 n gpmi _rdy 2 gpmi _ce3 n vddi o_em i vddi o_em i vddi o_em i emi_ d01 vss emi_ dqm0 vssi o_em i emi_ d07 m nnc lcd_ d06 vddi o33 vss nc gpmi _rdy 0 gpmi _ce0 n gpmi _rdy 1 gpmi _ce1 n emi_ a14 emi_ a07 emi_ ba2 vddi o_em i emi_ d03 vddi o_em i emi_ d00 vddi o33_ emi n p lcd_ d07 lcd_ d08 lcd_ d09 lcd_ rd_e lcd_ cs gpmi _ale gpmi _cle gpmi _wr n emi_ ce1n emi_ a09 vddi o_em i emi_ ce0n emi_ d04 vssi o_em i emi_ d02 vssi o_em i emi_ d05 p r lcd_ d10 lcd_ d11 lcd_ d17 lcd_ d20 lcd_ d23 gpmi _rdn gpmi _d05 gpmi _d02 emi_ a06 vssi o_em i emi_ a05 vssi o_em i vddi o_em i emi_ vref 0 vddi o_em iq emi_ rasn emi_ odt0 r t lcd_ d12 lcd_ d13 lcd_ d16 lcd_ d19 lcd_ d22 gpmi _d07 gpmi _d04 gpmi _d01 emi_ a13 emi_ a11 emi_ a03 emi_ ba1 emi_ cke vssi o_em i emi_ wen emi_ ba0 emi_ odt1 t u vss lcd_ d14 lcd_ d15 lcd_ d18 lcd_ d21 gpmi _d06 gpmi _d03 gpmi _d00 emi_ a08 emi_ a04 emi_ a12 emi_ a01 emi_ a10 emi_ a02 emi_ a00 emi_ casn vssi o_em i u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 67 4.6 i.mx283 ball map figure 47 shows the i.mx283 mapbga ball map. figure 47. 289-pin i.mx283 mapbga ball map 1234567891011121314151617 a vss nc ssp2_s ck ssp0_c md ssp0_d ata3 ssp0_s ck vddio3 3 usb1dp vss usb0d m pswitc h xtali vdd4p2 resetn batter y dcdc_l p dcdc_ gnd a b nc nc ssp2_m iso ssp0_d ata7 ssp0_d ata4 ssp0_d ata0 vss usb1d m debug usb0dp vssa2 xtalo vssa1 hsadc0 dcdc_b att dcdc_v dda dcdc_l n1 b c nc nc ssp2_m osi ssp2_s s0 ssp0_d ata5 ssp0_d ata1 i2c0_sc l lradc2 lradc1 testm ode rtc_xt alo vddxt al vdda1 lradc6 lradc0 vss dcdc_v ddio c d nc nc ssp2_s s1 ssp2_s s2 ssp0_d ata6 ssp0_d ata2 nc i2c0_sd a lradc3 ssp0_d etect rtc_xt ali jtag_t ms lradc4 jtag_t rst lradc5 vdd1p5 dcdc_v ddd d e nc enet_c lk nc enet0_ rx_en vss vddio3 3 saif0_s data0 saif1_s data0 pwm3 pwm4 jtag_t ck jtag_t di jtag_t do jtag_r tck vss vddio3 3 vdd5v e f enet0_ txd0 enet0_ txd1 nc enet0_ tx_en nc nc saif0_b itclk vddio1 8 vddio1 8 vddd vddd vddd emi_d1 4 vssio_ emi emi_d qm1 vssio_ emi emi_d1 5 f g nc nc vddio3 3 enet0_ mdc auart 0_rx saif0_l rclk saif0_ mclk vddio1 8 vddio1 8 vddd vddd vddd vddio_ emi emi_d1 0 vddio_ emi emi_d0 8 vddio_ emi g h enet0_ rxd0 enet0_ rxd1 vss enet0_ mdio auart 0_tx nc nc vddio3 3 vss vss vss vss emi_d1 2 vssio_ emi emi_d0 9 vss emi_d1 3 h j nc nc nc nc nc auart 0_cts auart 0_rts vddio3 3 vddio3 3 vddio3 3 vss vss vddio_ emiq emi_d1 1 vss emi_d qs1n emi_d qs1 j k lcd_w r_rwn lcd_d0 0 lcd_d0 1 auart 1_tx nc nc pwm0 pwm2 vss vss vss vddd emi_vr ef1 emi_dd r_ope vddio_ emiq emi_d qs0n emi_d qs0 k l nc lcd_d0 2 lcd_d0 3 auart 1_rx nc nc pwm1 nc gpmi_r esetn vss vss vssio_ emi vddio_ emi emi_d0 6 emi_dd r_ope emi_cl kn emi_cl k l m nc lcd_d0 4 lcd_d0 5 lcd_rs nc lcd_re set nc nc nc vddio_ emi vddio_ emi vddio_ emi emi_d0 1 vss emi_d qm0 vssio_ emi emi_d0 7 m n nc lcd_d0 6 vddio3 3 vss nc gpmi_r dy0 gpmi_c e0n gpmi_r dy1 gpmi_c e1n emi_a1 4 emi_a0 7 emi_ba 2 vddio_ emi emi_d0 3 vddio_ emi emi_d0 0 vddio3 3_emi n p lcd_d0 7 lcd_d0 8 lcd_d0 9 lcd_rd _e lcd_cs gpmi_a le gpmi_c le gpmi_ wrn emi_ce 1n emi_a0 9 vddio_ emi emi_ce 0n emi_d0 4 vssio_ emi emi_d0 2 vssio_ emi emi_d0 5 p r lcd_d1 0 lcd_d1 1 lcd_d1 7 lcd_d2 0 lcd_d2 3 gpmi_r dn gpmi_ d05 gpmi_ d02 emi_a0 6 vssio_ emi emi_a0 5 vssio_ emi vddio_ emi emi_vr ef0 vddio_ emiq emi_ra sn emi_o dt0 r t lcd_d1 2 lcd_d1 3 lcd_d1 6 lcd_d1 9 lcd_d2 2 gpmi_ d07 gpmi_ d04 gpmi_ d01 emi_a1 3 emi_a1 1 emi_a0 3 emi_ba 1 emi_ck e vssio_ emi emi_w en emi_ba 0 emi_o dt1 t u vss lcd_d1 4 lcd_d1 5 lcd_d1 8 lcd_d2 1 gpmi_ d06 gpmi_ d03 gpmi_ d00 emi_a0 8 emi_a0 4 emi_a1 2 emi_a0 1 emi_a1 0 emi_a0 2 emi_a0 0 emi_ca sn vssio_ emi u 1234567891011121314151617
i.mx28 applications processors data sh eet for consumer products, rev. 1 68 freescale semiconductor 4.7 i.mx280 ball map figure 48 shows the i.mx280 mapbga ball map. figure 48. 289-pin i.mx280 mapbga ball map 1234567891011121314151617 a vss nc ssp2_s ck ssp0_c md ssp0_d ata3 ssp0_s ck vddio3 3 usb1d p vss usb0d m pswitc h xtali vdd4p 2 resetn batter y dcdc_l p dcdc_ gnd a b nc nc ssp2_ miso ssp0_d ata7 ssp0_d ata4 ssp0_d ata0 vss usb1d m debug usb0d p vssa2 xtalo vssa1 hsadc 0 dcdc_ batt dcdc_ vdda dcdc_l n1 b c nc nc ssp2_ mosi ssp2_s s0 ssp0_d ata5 ssp0_d ata1 i2c0_sc l lradc2 lradc1 testm ode rtc_xt alo vddxt al vdda1 lradc6 lradc0 vss dcdc_ vddio c d nc nc ssp2_s s1 ssp2_s s2 ssp0_d ata6 ssp0_d ata2 nc i2c0_s da lradc3 ssp0_d etect rtc_xt ali jtag_t ms lradc4 jtag_t rst lradc5 vdd1p 5 dcdc_ vddd d e nc enet_c lk nc enet0_ rx_en vss vddio3 3 saif0_s data0 saif1_s data0 pwm3 pwm4 jtag_t ck jtag_t di jtag_t do jtag_r tck vss vddio3 3 vdd5v e f enet0_ txd0 enet0_ txd1 nc enet0_ tx_en nc nc saif0_ bitclk vddio1 8 vddio1 8 vddd vddd vddd emi_d1 4 vssio_ emi emi_d qm1 vssio_ emi emi_d1 5 f g nc nc vddio3 3 enet0_ mdc auart 0_rx saif0_l rclk saif0_ mclk vddio1 8 vddio1 8 vddd vddd vddd vddio_ emi emi_d1 0 vddio_ emi emi_d0 8 vddio_ emi g h enet0_ rxd0 enet0_ rxd1 vss enet0_ mdio auart 0_tx nc nc vddio3 3 vss vss vss vss emi_d1 2 vssio_ emi emi_d0 9 vss emi_d1 3 h j nc nc nc nc nc auart 0_cts auart 0_rts vddio3 3 vddio3 3 vddio3 3 vss vss vddio_ emiq emi_d1 1 vss emi_d qs1n emi_d qs1 j k etm_t clk etm_d a0 etm_d a1 auart 1_tx nc nc pwm0 pwm2 vss vss vss vddd emi_vr ef1 emi_d dr_op en vddio_ emiq emi_d qs0n emi_d qs0 k l nc etm_d a2 etm_d a3 auart 1_rx nc nc pwm1 nc gpmi_ resetn vss vss vssio_ emi vddio_ emi emi_d0 6 emi_d dr_op en_fb emi_cl kn emi_cl k l m nc etm_d a4 etm_d a5 gpio_b 1p26 nc nc nc nc nc vddio_ emi vddio_ emi vddio_ emi emi_d0 1 vss emi_d qm0 vssio_ emi emi_d0 7 m n nc etm_d a6 vddio3 3 vss nc gpmi_ rdy0 gpmi_ ce0n gpmi_ rdy1 gpmi_ ce1n emi_a1 4 emi_a0 7 emi_ba 2 vddio_ emi emi_d0 3 vddio_ emi emi_d0 0 vddio3 3_emi n p etm_d a7 nc nc etm_t ctl nc gpmi_ ale gpmi_ cle gpmi_ wrn emi_ce 1n emi_a0 9 vddio_ emi emi_ce 0n emi_d0 4 vssio_ emi emi_d0 2 vssio_ emi emi_d0 5 p r nc nc nc nc nc gpmi_ rdn gpmi_ d05 gpmi_ d02 emi_a0 6 vssio_ emi emi_a0 5 vssio_ emi vddio_ emi emi_vr ef0 vddio_ emiq emi_ra sn emi_o dt0 r t nc nc nc nc nc gpmi_ d07 gpmi_ d04 gpmi_ d01 emi_a1 3 emi_a1 1 emi_a0 3 emi_ba 1 emi_ck e vssio_ emi emi_w en emi_ba 0 emi_o dt1 t u vss nc nc nc nc gpmi_ d06 gpmi_ d03 gpmi_ d00 emi_a0 8 emi_a0 4 emi_a1 2 emi_a0 1 emi_a1 0 emi_a0 2 emi_a0 0 emi_ca sn vssio_ emi u 1234567891011121314151617
i.mx28 applications processors data sh eet for consumer products, rev. 1 freescale semiconductor 69 5 revision history table 67 summarizes revisions to this document. table 67. revision history rev. # date revision rev. 1 04/2011 ? updated section 1.1, ?device features .? ? added section 3.2, ?thermal characteristics .? ?in table 1, "ordering information," on page 3 , added two rows. ? updated table 2, "i.mx28 functional differences," on page 3 . ? updated table 4, "i.mx28 digital and analog modules," on page 6 . ?in table 8, "recommended power supply operating conditions," on page 13 , updated batt row. ? updated table 9, "operating temperature conditions," on page 13 . ? replaced the term ?dc characteristics? with ?power consumption? in the title and introduction of table 12, "power consumption," on page 14 . also changed dissipation to consumption in first row. ? updated table 26, "digital pin dc characteristics for gpio in 3.3-v mode," on page 21 . ? updated table 27, "digital pin dc characteristics for gpio in 1.8 v mode," on page 23 . ? updated and added a footnote to table 34, "ethernet pll specifications," on page 30 . ? updated ddr1 row of table 35, "emi command/address ac timing," on page 31 . ?in section 4.6, ?i.mx283 ball map,? replaced figure 47 . ? added section 4.7, ?i.mx280 ball map.? rev. 0 09/2010 initial release.
document number: imx28cec rev. 1 04/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale and the freescale logo are trademar ks of freescale semiconductor, inc. all other product or service names are th e property of their respective owners. arm is the registered trademark of arm limited. arm926ej-s, coresight, and etm9 are trademarks of arm limited. ieee 1588 and ieee 1149 are trademarks and ieee 802.3 is a registered trademark of the institut e of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. ? freescale semiconductor, inc., 2011. all rights reserved.

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